Why FSMs control complex sequential behavior in VHDL

Introduction

Finite State Machines (FSMs) help control complex sequences by breaking tasks into simple steps. They make sure each step happens in order and at the right time.

Designing a traffic light controller that changes lights in a fixed order.

Creating a vending machine that processes coins, selects items, and dispenses products step-by-step.

Building a digital lock that checks a sequence of button presses before unlocking.

Controlling a washing machine cycle with different stages like wash, rinse, and spin.

Syntax

VHDL

type state_type is (state1, state2, state3);
signal current_state, next_state : state_type;

process(clk)
begin
  if rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

process(current_state, inputs)
begin
  case current_state is
    when state1 =>
      if condition then
        next_state <= state2;
      else
        next_state <= state1;
      end if;
    when state2 =>
      -- next state logic
    when others =>
      next_state <= state1;
  end case;
end process;

FSMs use states to represent each step in a sequence.

Two processes are common: one to update the current state on clock edge, another to decide the next state based on inputs.

Examples

Defines three states for a simple FSM.

VHDL

type state_type is (IDLE, PROCESS, DONE);
signal current_state, next_state : state_type;

Updates the current state on each clock pulse.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

Decides the next state based on current state and input signal.

VHDL

process(current_state, start)
begin
  case current_state is
    when IDLE =>
      if start = '1' then
        next_state <= PROCESS;
      else
        next_state <= IDLE;
      end if;
    when PROCESS =>
      next_state <= DONE;
    when DONE =>
      next_state <= IDLE;
    when others =>
      next_state <= IDLE;
  end case;
end process;

Sample Program

This simple FSM waits in IDLE until 'start' is high, then moves to PROCESS, then to DONE, and back to IDLE. The output 'done' is high only in the DONE state.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity simple_fsm is
  port(
    clk : in std_logic;
    start : in std_logic;
    done : out std_logic
  );
end simple_fsm;

architecture behavior of simple_fsm is
  type state_type is (IDLE, PROCESS, DONE);
  signal current_state, next_state : state_type := IDLE;
begin
  -- State register process
  process(clk)
  begin
    if rising_edge(clk) then
      current_state <= next_state;
    end if;
  end process;

  -- Next state logic
  process(current_state, start)
  begin
    case current_state is
      when IDLE =>
        if start = '1' then
          next_state <= PROCESS;
        else
          next_state <= IDLE;
        end if;
      when PROCESS =>
        next_state <= DONE;
      when DONE =>
        next_state <= IDLE;
      when others =>
        next_state <= IDLE;
    end case;
  end process;

  -- Output logic
  done <= '1' when current_state = DONE else '0';
end behavior;

Important Notes

FSMs make complex sequences easier by splitting them into clear steps.

Always separate state update and next state logic for clarity.

Outputs can depend on the current state to show progress or results.

Summary

FSMs control sequences by moving through defined states step-by-step.

They help manage timing and order in digital designs.

Using FSMs makes complex behavior easier to design and understand.

Practice

1. Why are FSMs (Finite State Machines) used to control complex sequential behavior in VHDL designs?

easy

A. Because they organize behavior into clear, manageable states.

B. Because they make the circuit run faster than combinational logic.

C. Because they eliminate the need for clocks in the design.

D. Because they reduce the number of input signals required.

Solution

1. Step 1: Understand FSM purpose

   FSMs break down complex sequences into smaller states, making behavior easier to manage.

2. Step 2: Compare to other options

   FSMs do not inherently speed circuits, remove clocks, or reduce inputs; their main role is organizing states.

3. Final Answer:

   Because they organize behavior into clear, manageable states. -> Option A

4. Quick Check:

   FSMs = clear state management [OK]

Hint: FSMs split tasks into states for easy control [OK]

Common Mistakes:

• Thinking FSMs make circuits faster
• Believing FSMs remove clock signals
• Assuming FSMs reduce input count

2. Which VHDL code snippet correctly declares a simple FSM state type?

easy

A. type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type;

B. signal state : integer range 0 to 2;\ntype state_type is (IDLE, PROCESS, DONE);

C. type state_type is array (0 to 2) of std_logic;\nsignal state : state_type;

D. signal state : std_logic_vector(1 downto 0);\ntype state_type is (IDLE, PROCESS, DONE);

Solution

1. Step 1: Identify correct state type declaration

   type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type; correctly defines an enumerated type with states and a signal of that type.

2. Step 2: Check other options

   signal state : integer range 0 to 2;\ntype state_type is (IDLE, PROCESS, DONE); declares signal before type, which is invalid. type state_type is array (0 to 2) of std_logic;\nsignal state : state_type; uses array instead of enumeration. signal state : std_logic_vector(1 downto 0);\ntype state_type is (IDLE, PROCESS, DONE); mixes vector with enumeration incorrectly.

3. Final Answer:

   type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type; -> Option A

4. Quick Check:

   Correct enum type declaration = type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type; [OK]

Hint: Declare enum type before signal using it [OK]

Common Mistakes:

• Declaring signal before type
• Using arrays instead of enums for states
• Mixing std_logic_vector with enum states

3. Given the following VHDL FSM snippet, what is the next state when current state is PROCESS and input start = '0'?

type state_type is (IDLE, PROCESS, DONE);
signal state : state_type;

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        if start = '1' then
          state <= PROCESS;
        else
          state <= IDLE;
        end if;
      when PROCESS =>
        if start = '0' then
          state <= DONE;
        else
          state <= PROCESS;
        end if;
      when DONE =>
        state <= IDLE;
    end case;
  end if;
end process;

medium

A. IDLE

B. PROCESS

C. DONE

D. ERROR

Solution

1. Step 1: Analyze current state and input

   Current state is PROCESS and input start = '0'. According to code, PROCESS state moves to DONE if start = '0'.

2. Step 2: Determine next state

   Since start = '0', next state is DONE.

3. Final Answer:

   DONE -> Option C

4. Quick Check:

   PROCESS + start='0' = DONE [OK]

Hint: Follow case conditions for current state and input [OK]

Common Mistakes:

• Ignoring input value in state transition
• Confusing PROCESS and DONE states
• Assuming default next state is IDLE

4. Identify the error in this FSM process code snippet:

process(clk)
begin
  if clk'event and clk = '1' then
    case state is
      when IDLE =>
        if start = '1' then
          state <= PROCESS;
        end if;
      when PROCESS =>
        state <= DONE;
      when DONE =>
        state <= IDLE;
    end case;
  end if;
end process;

medium

A. Missing else branch in IDLE state causes latch inference.

B. Using clk'event instead of rising_edge(clk) is incorrect.

C. State transitions are not inside a clocked process.

D. No reset condition to initialize the state signal.

Solution

1. Step 1: Check clock event usage

   Using clk'event and clk = '1' is valid but less recommended than rising_edge(clk), so not an error.

2. Step 2: Look for reset signal

   The code lacks any reset condition to initialize the state signal, which can cause undefined behavior.

3. Final Answer:

   No reset condition to initialize the state signal. -> Option D

4. Quick Check:

   Missing reset = No reset condition to initialize the state signal. [OK]

Hint: Always include reset to set initial FSM state [OK]

Common Mistakes:

• Confusing clk'event with rising_edge(clk)
• Assuming else needed in every if
• Ignoring reset importance

5. You want to design an FSM in VHDL that controls a traffic light sequence: RED -> GREEN -> YELLOW -> RED. Which approach best uses FSMs to handle this complex sequential behavior?

hard

A. Use combinational logic only to switch lights based on input sensors.

B. Define states RED, GREEN, YELLOW and transition on a timer signal in a clocked process.

C. Use multiple independent signals toggling asynchronously for each light.

D. Write separate processes for each light color without state tracking.

Solution

1. Step 1: Identify FSM role in traffic light control

   FSMs manage sequences by defining states and transitions, perfect for timed traffic light changes.

2. Step 2: Evaluate options

   Define states RED, GREEN, YELLOW and transition on a timer signal in a clocked process. uses states and timer in a clocked process, matching FSM design principles. Others lack clear state control or timing.

3. Final Answer:

   Define states RED, GREEN, YELLOW and transition on a timer signal in a clocked process. -> Option B

4. Quick Check:

   FSM + timer = controlled traffic light sequence [OK]

Hint: Use states and timer in clocked process for sequences [OK]

Common Mistakes:

• Using only combinational logic for sequence
• Toggling signals asynchronously causing glitches
• Not tracking state leads to unpredictable behavior