Custom type definitions in packages in VHDL

Introduction

Custom types let you create your own data shapes to organize information clearly. Packages help share these types across many parts of your VHDL design.

When you want to group related signals into one named type, like a record for a bus.

When multiple design units need to use the same type to stay consistent.

When you want to define a set of named values, like an enumeration for states.

When you want to keep your code clean by separating type definitions from logic.

When you want to reuse types in different projects by importing the package.

Syntax

VHDL

package PackageName is
  type TypeName is (Value1, Value2, ...);  -- for enumeration
  type RecordName is record
    Field1 : Type1;
    Field2 : Type2;
  end record;
end PackageName;

package body PackageName is
  -- optional implementation details
end PackageName;

Packages contain type definitions inside the package declaration.

Use package body only if you have implementations like functions; for types, it's often empty.

Examples

This defines an enumeration type StateType with three named values.

VHDL

package MyTypes is
  type StateType is (IDLE, RUNNING, STOPPED);
end MyTypes;

This defines a record type DataBus grouping address and data signals.

VHDL

package BusTypes is
  type DataBus is record
    address : std_logic_vector(7 downto 0);
    data    : std_logic_vector(15 downto 0);
  end record;
end BusTypes;

Sample Program

This program defines custom types in a package and uses them in an entity. It reports the initial values of the signals.

VHDL

library ieee;
use ieee.std_logic_1164.all;

package MyTypes is
  type LightState is (OFF, ON);
  type SensorData is record
    temperature : integer;
    humidity    : integer;
  end record;
end MyTypes;

package body MyTypes is
  -- No implementation needed here
end MyTypes;

entity TestEntity is
end TestEntity;

architecture Behavioral of TestEntity is
  use work.MyTypes.all;
  signal light : LightState := OFF;
  signal sensor : SensorData := (temperature => 25, humidity => 60);
begin
  process
  begin
    report "Initial light state: " & LightState'image(light);
    report "Temperature: " & integer'image(sensor.temperature);
    report "Humidity: " & integer'image(sensor.humidity);
    wait;
  end process;
end Behavioral;

Important Notes

Always put your custom types in packages to reuse them easily.

Remember to use the package in your design units to access the types.

Enumeration types have a built-in function 'image to convert values to strings for reporting.

Summary

Custom types help organize data clearly in VHDL.

Packages let you share these types across your design.

Use use work.PackageName.all; to access types in your code.

Practice

1. What is the main purpose of defining custom types inside a VHDL package?

easy

A. To speed up the simulation time of the VHDL design

B. To restrict the use of variables only within a single architecture

C. To automatically generate test benches for the design

D. To create reusable and organized data structures accessible by multiple design units

Solution

1. Step 1: Understand the role of packages in VHDL

   Packages are used to group related declarations like types, constants, and subprograms for reuse.

2. Step 2: Identify the benefit of custom types in packages

   Custom types defined in packages can be shared across multiple design units, improving organization and reusability.

3. Final Answer:

   To create reusable and organized data structures accessible by multiple design units -> Option D

4. Quick Check:

   Custom types in packages = reusable and organized [OK]

Hint: Packages hold reusable types for multiple design parts [OK]

Common Mistakes:

• Thinking packages speed up simulation
• Believing packages restrict variable scope to one architecture
• Confusing packages with test bench generators

2. Which of the following is the correct syntax to declare a new enumeration type Color inside a package in VHDL?

easy

A. type Color is (Red, Green, Blue);

B. enum Color {Red, Green, Blue};

C. define Color = (Red, Green, Blue);

D. Color : enum (Red, Green, Blue);

Solution

1. Step 1: Recall VHDL enumeration type syntax

   In VHDL, enumeration types are declared using the keyword type followed by the type name and the list of values in parentheses.

2. Step 2: Match the syntax to the options

   type Color is (Red, Green, Blue); uses the correct VHDL syntax: type Color is (Red, Green, Blue); Other options use syntax from other languages or incorrect forms.

3. Final Answer:

   type Color is (Red, Green, Blue); -> Option A

4. Quick Check:

   VHDL enum syntax = type Name is (values); [OK]

Hint: VHDL enums start with 'type Name is (values);' [OK]

Common Mistakes:

• Using C-style enum syntax in VHDL
• Forgetting the 'type' keyword
• Using '=' instead of 'is' for type declaration

3. Given the package declaration:

package MyTypes is
  type StateType is (Idle, Busy, Done);
end package MyTypes;

And the following code inside an architecture:

use work.MyTypes.all;
signal current_state : StateType := Idle;

What is the initial value of current_state?

medium

A. Undefined

B. Busy

C. Idle

D. Done

Solution

1. Step 1: Understand the enumeration and signal declaration

   The enumeration StateType has values Idle, Busy, Done. The signal current_state is declared with initial value Idle.

2. Step 2: Identify the initial value assigned

   The signal is explicitly initialized to Idle, so its initial value is Idle.

3. Final Answer:

   Idle -> Option C

4. Quick Check:

   Signal initialized to Idle = Idle [OK]

Hint: Signal initialization sets starting value directly [OK]

Common Mistakes:

• Assuming default is first enum value without initialization
• Confusing signal declaration with variable declaration
• Thinking uninitialized signals default to Undefined

4. Consider this package declaration:

package MyPkg is
  type ModeType is (Auto, Manual);
end package MyPkg;

Assume use work.MyPkg.all; is properly included. Which of the following signal declarations inside an architecture will cause a compilation error?

medium

A. signal mode : ModeType := Manual;

B. signal mode : ModeType := Off;

C. signal mode : ModeType := Auto;

D. signal mode : ModeType;

Solution

1. Step 1: Check the enumeration values in the package

   The type ModeType has only two values: Auto and Manual.

2. Step 2: Analyze each code snippet for correctness

   signal mode : ModeType := Auto;: Correct initialization with valid value.
   signal mode : ModeType := Manual;: Correct initialization with valid value.
   signal mode : ModeType := Off;: Initialization with Off, which is not a valid enumeration value, causes a compilation error.
   signal mode : ModeType;: Declaration without initialization is allowed.

3. Final Answer:

   signal mode : ModeType := Off; -> Option B

4. Quick Check:

   Invalid enum value causes error = signal mode : ModeType := Off; [OK]

Hint: Enum values must match exactly declared names [OK]

Common Mistakes:

• Using undeclared enum values
• Thinking signals must always be initialized
• Confusing valid and invalid enumeration literals

5. You want to define a package with a record type Person that has a name as a string of 20 characters and an age as an integer. Which package declaration is correct and allows reuse in multiple architectures?

hard

A. package PersonPkg is
type Person is record
name : string(1 to 20);
age : integer;
end record;
end package PersonPkg;

B. package PersonPkg is
record Person {
name : string(1 to 20);
age : integer;
}
end package PersonPkg;

C. package PersonPkg is
type Person is array(1 to 20) of character;
age : integer;
end package PersonPkg;

D. package PersonPkg is
type Person is record
name : string(20);
age : integer;
end record;
end package PersonPkg;

Solution

1. Step 1: Understand record type syntax in VHDL packages

   Records are declared with type Name is record ... end record; inside a package for reuse.

2. Step 2: Check each option for correct syntax and type usage

   package PersonPkg is type Person is record name : string(1 to 20); age : integer; end record; end package PersonPkg; correctly declares a record with a string range and integer age.
   package PersonPkg is record Person { name : string(1 to 20); age : integer; } end package PersonPkg; uses incorrect syntax with curly braces, not valid in VHDL.
   package PersonPkg is type Person is array(1 to 20) of character; age : integer; end package PersonPkg; declares Person as an array but age is outside the record.
   package PersonPkg is type Person is record name : string(20); age : integer; end record; end package PersonPkg; uses string(20) which is invalid; string must have a range like (1 to 20).

3. Final Answer:

   package PersonPkg is type Person is record name : string(1 to 20); age : integer; end record; end package PersonPkg; -> Option A

4. Quick Check:

   Record with correct string range and integer = package PersonPkg is type Person is record name : string(1 to 20); age : integer; end record; end package PersonPkg; [OK]

Hint: Use 'string(1 to N)' for fixed-length strings in records [OK]

Common Mistakes:

• Using curly braces instead of VHDL record syntax
• Incorrect string type declaration without range
• Placing fields outside the record block