Sequence detector FSM in VHDL

Introduction

A sequence detector FSM finds a specific pattern of bits in a stream of input bits. It helps digital circuits recognize important signals.

Detecting a special code in a data stream, like a password or command.

Finding a pattern in communication signals to trigger an action.

Checking for errors by spotting known bit sequences.

Controlling devices that respond only when a certain bit pattern appears.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sequence_detector is
    port(
        clk     : in std_logic;
        reset   : in std_logic;
        data_in : in std_logic;
        detected: out std_logic
    );
end entity;

architecture Behavioral of sequence_detector is
    type state_type is (S0, S1, S2, S3); -- example states
    signal state, next_state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= S0;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    process(state, data_in)
    begin
        case state is
            when S0 =>
                if data_in = '1' then
                    next_state <= S1;
                else
                    next_state <= S0;
                end if;
            when S1 =>
                -- continue transitions
            when others =>
                next_state <= S0;
        end case;
    end process;

    detected <= '1' when state = S3 else '0';
end Behavioral;

States represent steps in recognizing the sequence.

Two processes: one for state update on clock, one for next state logic.

Examples

Define states for the FSM as an enumerated type.

VHDL

type state_type is (IDLE, S1, S2, DETECTED);
signal state, next_state : state_type;

Update the current state on clock edge or reset.

VHDL

process(clk, reset)
begin
    if reset = '1' then
        state <= IDLE;
    elsif rising_edge(clk) then
        state <= next_state;
    end if;
end process;

Decide next state based on current state and input.

VHDL

process(state, data_in)
begin
    case state is
        when IDLE =>
            if data_in = '1' then
                next_state <= S1;
            else
                next_state <= IDLE;
            end if;
        when S1 =>
            -- next transitions
        when others =>
            next_state <= IDLE;
    end case;
end process;

Sample Program

This FSM detects the sequence '101' on the input data_in. When it sees '1', then '0', then '1' in order, it sets detected to '1' for one clock cycle.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sequence_detector is
    port(
        clk     : in std_logic;
        reset   : in std_logic;
        data_in : in std_logic;
        detected: out std_logic
    );
end entity;

architecture Behavioral of sequence_detector is
    type state_type is (S0, S1, S2, S3);
    signal state, next_state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= S0;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    process(state, data_in)
    begin
        case state is
            when S0 =>
                if data_in = '1' then
                    next_state <= S1;
                else
                    next_state <= S0;
                end if;
            when S1 =>
                if data_in = '0' then
                    next_state <= S2;
                else
                    next_state <= S1;
                end if;
            when S2 =>
                if data_in = '1' then
                    next_state <= S3;
                else
                    next_state <= S0;
                end if;
            when S3 =>
                next_state <= S0;
            when others =>
                next_state <= S0;
        end case;
    end process;

    detected <= '1' when state = S3 else '0';
end Behavioral;

Important Notes

Resetting the FSM sets it back to the start state.

The output detected is high only when the full sequence is found.

Make sure clock and reset signals are connected properly in your design.

Summary

A sequence detector FSM watches input bits to find a pattern.

It uses states to remember progress in matching the sequence.

VHDL uses processes and state types to build the FSM logic.

Practice

1. What is the main purpose of a sequence detector FSM in VHDL?

easy

A. To perform arithmetic operations

B. To generate random numbers

C. To detect a specific pattern of bits in a serial input stream

D. To store large amounts of data

Solution

1. Step 1: Understand FSM role

   A sequence detector FSM is designed to watch input bits and identify a particular pattern.

2. Step 2: Match purpose with options

   Only To detect a specific pattern of bits in a serial input stream describes detecting a pattern in a bit stream, which matches the FSM's purpose.

3. Final Answer:

   To detect a specific pattern of bits in a serial input stream -> Option C

4. Quick Check:

   Sequence detector FSM = Pattern detection [OK]

Hint: FSMs track input patterns step-by-step [OK]

Common Mistakes:

• Confusing FSM with memory storage
• Thinking FSM generates data
• Assuming FSM does math operations

2. Which VHDL construct is typically used to represent the states in a sequence detector FSM?

easy

A. signal

B. type (enumeration)

C. process

D. variable

Solution

1. Step 1: Identify how states are defined

   States in FSMs are usually defined as an enumerated type listing all possible states.

2. Step 2: Match with VHDL constructs

   Only 'type (enumeration)' fits this use, as it defines named states clearly.

3. Final Answer:

   type (enumeration) -> Option B

4. Quick Check:

   States = enumerated type [OK]

Hint: Use enumerated types to name FSM states clearly [OK]

Common Mistakes:

• Using signal or variable to define states directly
• Confusing process with state definition
• Not using enumeration for states

3. Given this VHDL snippet for a sequence detector FSM, what is the output when input sequence is 1,0,1,1?

type state_type is (S0, S1, S2, S3);
signal state: state_type := S0;
signal detected: std_logic := '0';

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when S0 =>
        if input_bit = '1' then
          state <= S1;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S1 =>
        if input_bit = '0' then
          state <= S2;
        else
          state <= S1;
        end if;
        detected <= '0';
      when S2 =>
        if input_bit = '1' then
          state <= S3;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S3 =>
        detected <= '1';
        state <= S0;
    end case;
  end if;
end process;

medium

A. detected = '1' after the second input

B. detected = '1' after the third input

C. detected = '0' for all inputs

D. detected = '1' after the fourth input

Solution

1. Step 1: Trace FSM states with inputs

   Input sequence: 1 -> S0 to S1, detected=0; 0 -> S1 to S2, detected=0; 1 -> S2 to S3, detected=0; 1 -> S3 outputs detected=1 and resets to S0.

2. Step 2: Identify when detection occurs

   Detection signal '1' is set only in state S3, which happens after the fourth input.

3. Final Answer:

   detected = '1' after the fourth input -> Option D

4. Quick Check:

   Detection on full pattern completion = after 4th input [OK]

Hint: Trace states stepwise with inputs to find detection timing [OK]

Common Mistakes:

• Assuming detection happens too early
• Ignoring state reset after detection
• Confusing input bits with states

4. Identify the error in this VHDL FSM snippet for a sequence detector:

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when S0 =>
        if input_bit = '1' then
          state <= S1;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S1 =>
        if input_bit = '0' then
          state <= S2;
        else
          state <= S0; -- Error here
        end if;
        detected <= '0';
      when S2 =>
        if input_bit = '1' then
          state <= S3;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S3 =>
        detected <= '1';
        state <= S0;
    end case;
  end if;
end process;

medium

A. Resetting to S0 on wrong input in S1 breaks overlapping detection

B. Missing clock sensitivity list

C. Detected signal should be '1' in all states

D. State S3 is not defined

Solution

1. Step 1: Analyze state transitions in S1

   Resetting to S0 on wrong input in S1 prevents the FSM from detecting overlapping sequences.

2. Step 2: Understand impact on sequence detection

   Proper overlapping detection requires transitioning to S1 or another state, not always S0, to catch patterns starting inside previous ones.

3. Final Answer:

   Resetting to S0 on wrong input in S1 breaks overlapping detection -> Option A

4. Quick Check:

   Overlapping detection needs careful state transitions [OK]

Hint: Check if FSM allows overlapping pattern detection [OK]

Common Mistakes:

• Ignoring overlapping sequences
• Assuming detected signal always '1'
• Forgetting clock edge sensitivity

5. You want to design a sequence detector FSM in VHDL that detects overlapping occurrences of the pattern "1011". Which approach correctly handles overlapping detection?

hard

A. After detecting full pattern, transition to the state representing the last '1' to allow overlap

B. Reset to initial state after detection to start fresh

C. Use a counter instead of states to track bits

D. Ignore overlapping sequences to simplify design

Solution

1. Step 1: Understand overlapping detection

   To detect overlapping patterns, FSM must not reset fully but keep track of partial matches.

2. Step 2: Choose correct state transition

   Transitioning to the state representing the last matched bit (here, last '1') allows the FSM to continue detecting overlapping sequences.

3. Final Answer:

   After detecting full pattern, transition to the state representing the last '1' to allow overlap -> Option A

4. Quick Check:

   Overlap detection = partial state retention [OK]

Hint: Keep FSM in partial match state after detection for overlaps [OK]

Common Mistakes:

• Resetting FSM fully after detection
• Using counters instead of states
• Ignoring overlapping patterns