BCD counter design in VHDL

Introduction

A BCD counter counts from 0 to 9 in binary form. It helps in digital clocks, calculators, and other devices that show numbers.

When you want to count digits from 0 to 9 repeatedly.

To build a digital clock that shows seconds or minutes.

In calculators to keep track of entered numbers.

When designing simple number displays using seven-segment LEDs.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_counter is
    port(
        clk   : in std_logic;
        reset : in std_logic;
        count : out std_logic_vector(3 downto 0)
    );
end bcd_counter;

architecture behavioral of bcd_counter is
    signal cnt : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            cnt <= (others => '0');
        elsif rising_edge(clk) then
            if cnt = 9 then
                cnt <= (others => '0');
            else
                cnt <= cnt + 1;
            end if;
        end if;
    end process;
    count <= std_logic_vector(cnt);
end behavioral;

The counter uses a 4-bit unsigned signal to hold values 0 to 9.

When the count reaches 9, it resets to 0 on the next clock.

Examples

This checks if the count is 9, then resets to 0; otherwise, it adds 1.

VHDL

if cnt = 9 then
    cnt <= (others => '0');
else
    cnt <= cnt + 1;
end if;

This converts the unsigned count to a std_logic_vector to output.

VHDL

count <= std_logic_vector(cnt);

Sample Program

This program defines a BCD counter that counts from 0 to 9 and resets. The testbench simulates clock and reset signals and prints the count value on each clock rising edge.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_counter is
    port(
        clk   : in std_logic;
        reset : in std_logic;
        count : out std_logic_vector(3 downto 0)
    );
end bcd_counter;

architecture behavioral of bcd_counter is
    signal cnt : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            cnt <= (others => '0');
        elsif rising_edge(clk) then
            if cnt = 9 then
                cnt <= (others => '0');
            else
                cnt <= cnt + 1;
            end if;
        end if;
    end process;
    count <= std_logic_vector(cnt);
end behavioral;

-- Testbench to simulate the counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_bcd_counter is
end tb_bcd_counter;

architecture testbench of tb_bcd_counter is
    signal clk   : std_logic := '0';
    signal reset : std_logic := '1';
    signal count : std_logic_vector(3 downto 0);

    constant clk_period : time := 10 ns;
begin
    uut: entity work.bcd_counter
        port map(
            clk => clk,
            reset => reset,
            count => count
        );

    clk_process : process
    begin
        while now < 110 ns loop
            clk <= '0';
            wait for clk_period / 2;
            clk <= '1';
            wait for clk_period / 2;
        end loop;
        wait;
    end process;

    stim_proc: process
    begin
        wait for 15 ns;
        reset <= '0';
        wait for 100 ns;
        wait;
    end process;

    monitor_proc: process(clk)
    begin
        if rising_edge(clk) then
            report "Count = " & integer'image(to_integer(unsigned(count)));
        end if;
    end process;
end testbench;

Important Notes

Use the unsigned type for easy arithmetic on bits.

Resetting the counter ensures it starts from zero safely.

Simulation reports help verify the counter works as expected.

Summary

A BCD counter counts from 0 to 9 in binary form.

It resets to 0 after reaching 9 to repeat the cycle.

VHDL uses processes and signals to describe this behavior clearly.

Practice

1. What is the main function of a BCD counter in digital circuits?

easy

A. To count decimal digits from 0 to 9 in binary form

B. To count binary numbers from 0 to 15

C. To convert analog signals to digital

D. To multiply two binary numbers

Solution

1. Step 1: Understand BCD counting

   A BCD counter counts decimal digits 0 through 9 using binary representation.

2. Step 2: Differentiate from binary counters

   Unlike a binary counter that counts up to 15 (4 bits), BCD resets after 9 to represent decimal digits.

3. Final Answer:

   To count decimal digits from 0 to 9 in binary form -> Option A

4. Quick Check:

   BCD counter counts 0-9 decimal digits [OK]

Hint: BCD counters count decimal digits 0-9 in binary [OK]

Common Mistakes:

• Confusing BCD with binary counters counting 0-15
• Thinking BCD converts analog signals
• Assuming BCD performs arithmetic multiplication

2. Which of the following is the correct VHDL syntax to declare a 4-bit signal named count for a BCD counter?

easy

A. signal count : integer range 0 to 15;

B. signal count : std_logic_vector(3 to 0);

C. signal count : bit_vector(3 to 0);

D. signal count : std_logic_vector(3 downto 0);

Solution

1. Step 1: Identify correct vector type and range

   For a 4-bit signal, std_logic_vector(3 downto 0) is standard and correct.

2. Step 2: Check other options for errors

   Integer range 0 to 15 uses integer type, not vector; bit_vector(3 to 0) uses invalid range direction; std_logic_vector(3 to 0) uses invalid range direction.

3. Final Answer:

   signal count : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   4-bit std_logic_vector with downto 0 indexing [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit signals [OK]

Common Mistakes:

• Using integer instead of std_logic_vector for bit signals
• Incorrect vector range direction
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a BCD counter, what will be the value of count after the 10th rising clock edge?

process(clk)
begin
  if rising_edge(clk) then
    if count = "1001" then
      count <= "0000";
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. "1010"

B. "0000"

C. "1001"

D. "0001"

Solution

1. Step 1: Understand counting behavior

   The counter increments each clock edge until it reaches "1001" (decimal 9), then resets to "0000".

2. Step 2: Count 10 clock edges

   After 9 increments, count is "1001"; on the 10th clock, it resets to "0000".

3. Final Answer:

   "0000" -> Option B

4. Quick Check:

   BCD resets after 9, so 10th count is 0 [OK]

Hint: BCD resets to 0 after 9 counts [OK]

Common Mistakes:

• Assuming count continues to "1010" which is invalid BCD
• Forgetting reset condition at 9
• Confusing binary and decimal counting

4. Identify the error in this VHDL BCD counter snippet:

process(clk)
begin
  if rising_edge(clk) then
    if count = "1010" then
      count <= "0000";
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. The process is missing a sensitivity list

B. The signal count is not declared

C. The reset condition should check for "1001" instead of "1010"

D. The increment operation is invalid for std_logic_vector

Solution

1. Step 1: Check reset condition value

   BCD counts 0 to 9, so reset should occur at "1001" (decimal 9), not "1010" (decimal 10).

2. Step 2: Verify other parts

   Signal declaration and sensitivity list are correct; increment on std_logic_vector requires numeric conversion but is often handled by libraries.

3. Final Answer:

   The reset condition should check for "1001" instead of "1010" -> Option C

4. Quick Check:

   BCD resets at 9 ("1001"), not 10 ("1010") [OK]

Hint: Reset BCD at "1001" (decimal 9), not "1010" [OK]

Common Mistakes:

• Using "1010" as reset condition instead of "1001"
• Ignoring numeric conversion for increment
• Confusing sensitivity list requirements

5. You want to design a BCD counter in VHDL that counts from 0 to 9 and then resets to 0. Which approach correctly implements this behavior?

hard

A. Use a 4-bit std_logic_vector, increment it each clock, and reset to "0000" when it reaches "1001"

B. Use an integer signal from 0 to 15 and reset at 9

C. Use a 4-bit std_logic_vector and reset at "1111"

D. Use a 3-bit std_logic_vector and reset at "1001"

Solution

1. Step 1: Choose correct signal type and size

   A 4-bit std_logic_vector is needed to represent digits 0 to 9 in BCD.

2. Step 2: Implement correct reset condition

   Reset should occur when count reaches "1001" (decimal 9), then reset to "0000" to repeat counting.

3. Final Answer:

   Use a 4-bit std_logic_vector, increment it each clock, and reset to "0000" when it reaches "1001" -> Option A

4. Quick Check:

   4-bit vector + reset at 9 = correct BCD counter [OK]

Hint: Use 4-bit vector and reset at "1001" for BCD [OK]

Common Mistakes:

• Using integer range 0-15 instead of 0-9
• Resetting at wrong binary value like "1111"
• Using 3-bit vector which can't hold 0-9