Mealy machine implementation in VHDL - Time & Space Complexity

Time Complexity: Mealy machine implementation

O(n)

Understanding Time Complexity

When we write a Mealy machine in VHDL, it is important to understand how the time it takes to process inputs grows as the inputs or states increase.

We want to know how the number of steps changes when the machine handles more inputs or states.

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

library ieee;
use ieee.std_logic_1164.all;

entity mealy is
  port(clk: in std_logic; input: in std_logic; output: out std_logic);
end mealy;

architecture behavior of mealy is
  type state_type is (S0, S1);
  signal state: state_type := S0;
begin
  process(clk)
  begin
    if rising_edge(clk) then
      case state is
        when S0 =>
          if input = '1' then
            output <= '1';
            state <= S1;
          else
            output <= '0';
            state <= S0;
          end if;
        when S1 =>
          output <= '0';
          state <= S0;
      end case;
    end if;
  end process;
end behavior;

This code implements a simple Mealy machine with two states that changes output and state based on input at each clock cycle.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The process triggered on each clock rising edge that checks the current state and input to decide output and next state.
• How many times: This operation runs once every clock cycle, repeating indefinitely as the clock ticks.

How Execution Grows With Input

Each clock cycle, the machine performs a fixed number of steps to check state and input and update output and state.

Input Size (n)	Approx. Operations
10	10 steps (one per clock cycle)
100	100 steps
1000	1000 steps

Pattern observation: The number of operations grows directly with the number of clock cycles or inputs processed, staying constant per cycle.

Final Time Complexity

Time Complexity: O(n)

This means the time to process inputs grows linearly with the number of inputs or clock cycles.

Common Mistake

[X] Wrong: "The Mealy machine takes more time as the number of states increases because it loops over all states each cycle."

[OK] Correct: The machine only checks the current state each cycle, not all states. So time per cycle stays the same regardless of total states.

Interview Connect

Understanding how hardware state machines handle inputs step-by-step helps you explain efficient designs and timing in real projects.

Self-Check

"What if we added nested loops inside the process to check multiple inputs per cycle? How would the time complexity change?"

Practice

1.

What is the key characteristic of a Mealy machine in VHDL?

Output depends on:

easy

A. Only next state

B. Only current state

C. Only previous input

D. Current state and current input

Solution

1. Step 1: Understand Mealy machine output logic

   Mealy machine outputs depend on both the current state and the current input signals.

2. Step 2: Compare with other machine types

   Unlike Moore machines, which depend only on the current state, Mealy machines also consider inputs for output.

3. Final Answer:

   Current state and current input -> Option D

4. Quick Check:

   Mealy output = state + input [OK]

Hint: Remember Mealy output changes immediately with input [OK]

Common Mistakes:

• Thinking output depends only on state
• Confusing Mealy with Moore machine
• Ignoring input signals in output logic

2.

Which VHDL code snippet correctly declares a Mealy machine state process sensitive to clock and reset?

process(_____)
begin
  if reset = '1' then
    state <= idle;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

easy

A. clk, reset

B. clk

C. reset

D. clk, input

Solution

1. Step 1: Identify signals controlling state updates

   The process must be sensitive to clock and asynchronous reset signals to update state properly.

2. Step 2: Confirm sensitivity list correctness

   Including both clk and reset ensures the process triggers on clock edges and reset changes.

3. Final Answer:

   clk, reset -> Option A

4. Quick Check:

   Sensitivity list = clk + reset [OK]

Hint: State process needs clock and reset sensitivity [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Including input signals unnecessarily
• Using only clock without reset

3.

Given this Mealy machine output process snippet, what is the output when state = S1 and input = '1'?

process(state, input)
begin
  case state is
    when S0 => output <= '0';
    when S1 =>
      if input = '1' then
        output <= '1';
      else
        output <= '0';
      end if;
    when others => output <= '0';
  end case;
end process;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Identify current state and input

   The state is S1 and input is '1'.

2. Step 2: Follow process logic for state S1

   For S1, if input is '1', output is assigned '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   State S1 + input '1' = output '1' [OK]

Hint: Check state and input conditions carefully [OK]

Common Mistakes:

• Ignoring input condition inside state
• Assuming output always '0'
• Confusing state names

4.

Identify the error in this Mealy machine next state process:

process(clk, reset)
begin
  if reset = '1' then
    state <= S0;
  elsif rising_edge(clk) then
    case state is
      when S0 => next_state <= S1;
      when S1 => next_state <= S2;
      when others => next_state <= S0;
    end case;
  end if;
end process;

medium

A. Missing input sensitivity in process

B. Assigning next_state inside clocked process

C. Using next_state instead of state for updates

D. No error, code is correct

Solution

1. Step 1: Understand state update logic

   The clocked process should update the current state, not next_state.

2. Step 2: Identify incorrect assignment

   Assigning next_state inside the clocked process is incorrect; state must be updated on clock edge.

3. Final Answer:

   Assigning next_state inside clocked process -> Option B

4. Quick Check:

   Clocked process updates state, not next_state [OK]

Hint: Update current state on clock, next_state in combinational [OK]

Common Mistakes:

• Updating next_state in clocked process
• Confusing state and next_state signals
• Ignoring reset signal

5.

You want to implement a Mealy machine in VHDL that outputs '1' only when the input sequence '101' is detected. Which approach correctly combines state and input for output logic?

hard

A. Use input only in sensitivity list; output depends only on input

B. Use only state in sensitivity list; output depends only on state

C. Use a process with state and input in sensitivity list; output depends on both current state and input

D. Use asynchronous reset to set output directly

Solution

1. Step 1: Understand Mealy machine output requirements

   Output depends on detecting input sequence and current state, so both must be considered.

2. Step 2: Implement output logic in process sensitive to state and input

   Including both in sensitivity list ensures output updates immediately when input or state changes.

3. Step 3: Confirm output depends on current state and input

   This matches Mealy machine behavior for sequence detection.

4. Final Answer:

   Use a process with state and input in sensitivity list; output depends on both current state and input -> Option C

5. Quick Check:

   Output = state + input for sequence detection [OK]

Hint: Output depends on state and input for sequence detection [OK]

Common Mistakes:

• Ignoring input in output logic
• Using Moore machine style output
• Relying only on asynchronous reset for output