Mealy machine implementation in VHDL - Mini Project: Build & Apply

Mealy Machine Implementation in VHDL

📖 Scenario: You are designing a simple Mealy state machine in VHDL to detect a specific input pattern on a digital signal. This machine will output a signal based on the current state and input.

🎯 Goal: Build a Mealy machine in VHDL that detects when the input sequence '10' occurs and outputs a high signal 1 only during the transition when the pattern is detected.

📋 What You'll Learn

Create a VHDL entity and architecture for the Mealy machine

Define states using an enumerated type

Use a process sensitive to clock and reset signals

Implement state transitions and output logic based on input

Output should be high only when the pattern '10' is detected

💡 Why This Matters

🌍 Real World

Mealy machines are used in digital circuits to detect patterns or control sequences based on inputs and current states, such as in communication protocols or control systems.

💼 Career

Understanding Mealy machine implementation in VHDL is essential for FPGA and ASIC design engineers working on digital logic design and embedded systems.

1

Define the VHDL entity and states

Write the VHDL code to define an entity called MealyDetector with inputs clk, reset, and inp (all std_logic), and output outp (std_logic). Then, inside the architecture, define a type state_type with states IDLE and ONE_DETECTED. Declare signals current_state and next_state of type state_type.

VHDL

-- Your code here

Hint

Start by declaring the entity with the specified ports. Then define the states as an enumerated type and declare signals for current and next states.

2

Add synchronous process for state updates

Inside the architecture, add a process sensitive to clk and reset. On reset (when reset = '1'), set current_state to IDLE. On the rising edge of clk, update current_state to next_state.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MealyDetector is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        inp : in std_logic;
        outp : out std_logic
    );
end MealyDetector;

architecture Behavioral of MealyDetector is
    type state_type is (IDLE, ONE_DETECTED);
    signal current_state, next_state : state_type;
begin
    -- Add synchronous process for state updates
    -- Your code here
end Behavioral;

Hint

Use a process with clk and reset in sensitivity list. On reset, assign IDLE to current_state. On clock rising edge, assign next_state to current_state.

3

Implement next state logic and output logic

Add a combinational process sensitive to current_state and inp. Inside, use a case statement on current_state. For IDLE, if inp = '1', set next_state to ONE_DETECTED and outp to '0', else stay in IDLE and outp to '0'. For ONE_DETECTED, if inp = '0', set next_state to IDLE and outp to '1' (pattern detected), else stay in ONE_DETECTED and outp to '0'.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MealyDetector is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        inp : in std_logic;
        outp : out std_logic
    );
end MealyDetector;

architecture Behavioral of MealyDetector is
    type state_type is (IDLE, ONE_DETECTED);
    signal current_state, next_state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= IDLE;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    -- Add combinational process for next_state and outp
    -- Your code here
end Behavioral;

Hint

Use a process sensitive to current_state and inp. Use a case statement for states. Set next_state and outp according to the input and current state.

4

Test and display the output

Add a simple testbench process inside the architecture (optional) or write a print statement to display the output signal outp changes. For this project, just write -- Simulation or testbench is recommended to verify output. Then, write report "Mealy machine implemented successfully"; to confirm the design compiles.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MealyDetector is
    Port (
        clk : in std_logic;
        reset : in std_logic;
        inp : in std_logic;
        outp : out std_logic
    );
end MealyDetector;

architecture Behavioral of MealyDetector is
    type state_type is (IDLE, ONE_DETECTED);
    signal current_state, next_state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state 
                if inp = '1' then
                    next_state 
                if inp = '0' then
                    next_state <= IDLE;
                    outp <= '1';
                else
                    next_state <= ONE_DETECTED;
                    outp <= '0';
                end if;
        end case;
    end process;
    -- Your code here
end Behavioral;

Hint

Use a report statement to confirm the design compiles. Testing is recommended but optional here.

Practice

1.

What is the key characteristic of a Mealy machine in VHDL?

Output depends on:

easy

A. Only next state

B. Only current state

C. Only previous input

D. Current state and current input

Solution

1. Step 1: Understand Mealy machine output logic

   Mealy machine outputs depend on both the current state and the current input signals.

2. Step 2: Compare with other machine types

   Unlike Moore machines, which depend only on the current state, Mealy machines also consider inputs for output.

3. Final Answer:

   Current state and current input -> Option D

4. Quick Check:

   Mealy output = state + input [OK]

Hint: Remember Mealy output changes immediately with input [OK]

Common Mistakes:

• Thinking output depends only on state
• Confusing Mealy with Moore machine
• Ignoring input signals in output logic

2.

Which VHDL code snippet correctly declares a Mealy machine state process sensitive to clock and reset?

process(_____)
begin
  if reset = '1' then
    state <= idle;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

easy

A. clk, reset

B. clk

C. reset

D. clk, input

Solution

1. Step 1: Identify signals controlling state updates

   The process must be sensitive to clock and asynchronous reset signals to update state properly.

2. Step 2: Confirm sensitivity list correctness

   Including both clk and reset ensures the process triggers on clock edges and reset changes.

3. Final Answer:

   clk, reset -> Option A

4. Quick Check:

   Sensitivity list = clk + reset [OK]

Hint: State process needs clock and reset sensitivity [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Including input signals unnecessarily
• Using only clock without reset

3.

Given this Mealy machine output process snippet, what is the output when state = S1 and input = '1'?

process(state, input)
begin
  case state is
    when S0 => output <= '0';
    when S1 =>
      if input = '1' then
        output <= '1';
      else
        output <= '0';
      end if;
    when others => output <= '0';
  end case;
end process;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Identify current state and input

   The state is S1 and input is '1'.

2. Step 2: Follow process logic for state S1

   For S1, if input is '1', output is assigned '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   State S1 + input '1' = output '1' [OK]

Hint: Check state and input conditions carefully [OK]

Common Mistakes:

• Ignoring input condition inside state
• Assuming output always '0'
• Confusing state names

4.

Identify the error in this Mealy machine next state process:

process(clk, reset)
begin
  if reset = '1' then
    state <= S0;
  elsif rising_edge(clk) then
    case state is
      when S0 => next_state <= S1;
      when S1 => next_state <= S2;
      when others => next_state <= S0;
    end case;
  end if;
end process;

medium

A. Missing input sensitivity in process

B. Assigning next_state inside clocked process

C. Using next_state instead of state for updates

D. No error, code is correct

Solution

1. Step 1: Understand state update logic

   The clocked process should update the current state, not next_state.

2. Step 2: Identify incorrect assignment

   Assigning next_state inside the clocked process is incorrect; state must be updated on clock edge.

3. Final Answer:

   Assigning next_state inside clocked process -> Option B

4. Quick Check:

   Clocked process updates state, not next_state [OK]

Hint: Update current state on clock, next_state in combinational [OK]

Common Mistakes:

• Updating next_state in clocked process
• Confusing state and next_state signals
• Ignoring reset signal

5.

You want to implement a Mealy machine in VHDL that outputs '1' only when the input sequence '101' is detected. Which approach correctly combines state and input for output logic?

hard

A. Use input only in sensitivity list; output depends only on input

B. Use only state in sensitivity list; output depends only on state

C. Use a process with state and input in sensitivity list; output depends on both current state and input

D. Use asynchronous reset to set output directly

Solution

1. Step 1: Understand Mealy machine output requirements

   Output depends on detecting input sequence and current state, so both must be considered.

2. Step 2: Implement output logic in process sensitive to state and input

   Including both in sensitivity list ensures output updates immediately when input or state changes.

3. Step 3: Confirm output depends on current state and input

   This matches Mealy machine behavior for sequence detection.

4. Final Answer:

   Use a process with state and input in sensitivity list; output depends on both current state and input -> Option C

5. Quick Check:

   Output = state + input for sequence detection [OK]

Hint: Output depends on state and input for sequence detection [OK]

Common Mistakes:

• Ignoring input in output logic
• Using Moore machine style output
• Relying only on asynchronous reset for output