Case statement in process in VHDL

Introduction

A case statement helps you choose one action from many options based on a value. It makes your code clear and easy to read.

When you want to do different things depending on a signal's value inside a process.

When you have multiple conditions to check, and each leads to a different result.

When you want to replace many if-else statements with a cleaner way.

When designing digital circuits that react differently to input codes.

When you want to handle all possible values of a signal explicitly.

Syntax

VHDL

process(signal_name)
begin
  case signal_name is
    when value1 =>
      -- statements
    when value2 =>
      -- statements
    when others =>
      -- statements for all other values
  end case;
end process;

The case statement must be inside a process.

Use when others to cover any values not listed explicitly.

Examples

This example sets output based on a 2-bit selector sel. If sel is "00", output is '0'; if "01", output is '1'; otherwise, output is high impedance 'Z'.

VHDL

process(sel)
begin
  case sel is
    when "00" => output <= '0';
    when "01" => output <= '1';
    when others => output <= 'Z';
  end case;
end process;

This example changes next_state based on the current state. It cycles through states IDLE, READ, and WRITE.

VHDL

process(state)
begin
  case state is
    when IDLE => next_state <= READ;
    when READ => next_state <= WRITE;
    when WRITE => next_state <= IDLE;
    when others => next_state <= IDLE;
  end case;
end process;

Sample Program

This VHDL program lights up one LED out of four based on the 2-bit input sel. Each value of sel turns on a different LED.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity case_example is
  port(
    sel : in std_logic_vector(1 downto 0);
    led : out std_logic_vector(3 downto 0)
  );
end case_example;

architecture Behavioral of case_example is
begin
  process(sel)
  begin
    case sel is
      when "00" => led <= "0001";
      when "01" => led <= "0010";
      when "10" => led <= "0100";
      when "11" => led <= "1000";
      when others => led <= "0000";
    end case;
  end process;
end Behavioral;

Important Notes

Always include when others to avoid incomplete case warnings.

Case statements in VHDL are checked for completeness by the compiler.

Case statements improve readability compared to many if-else statements.

Summary

Use case inside a process to select actions based on a signal's value.

Include when others to handle unexpected values safely.

Case statements make your VHDL code cleaner and easier to understand.

Practice

1. What is the main purpose of a case statement inside a VHDL process?

easy

A. To select actions based on the value of a signal

B. To declare new signals inside the process

C. To loop through a range of values

D. To assign default values to all signals

Solution

1. Step 1: Understand the role of case statement

   The case statement chooses different actions depending on the value of a signal.

2. Step 2: Compare with other options

   Declaring signals, looping, or assigning defaults are not the main purpose of case.

3. Final Answer:

   To select actions based on the value of a signal -> Option A

4. Quick Check:

   Case statement = select actions by signal value [OK]

Hint: Case picks actions by signal value inside process [OK]

Common Mistakes:

• Thinking case declares signals
• Confusing case with loops
• Assuming case assigns default values

2. Which of the following is the correct syntax to start a case statement inside a VHDL process for signal sel?

easy

A. switch sel is

B. case (sel) then

C. if sel then

D. case sel is

Solution

1. Step 1: Recall VHDL case syntax

   The correct syntax to start a case statement is case signal_name is.

2. Step 2: Check each option

   case sel is matches the correct syntax. Options A, B, and D are incorrect VHDL syntax.

3. Final Answer:

   case sel is -> Option D

4. Quick Check:

   Correct case syntax = "case signal is" [OK]

Hint: Use 'case signal is' to start a case statement [OK]

Common Mistakes:

• Using 'switch' instead of 'case'
• Adding parentheses or 'then' incorrectly
• Confusing case with if statement

3. Given the following VHDL process, what will be the value of out_signal when sel = "10"?

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when "10" => out_signal <= '0';
    when others => out_signal <= '1';
  end case;
end process;

medium

A. '1'

B. Syntax error

C. '0'

D. Undefined

Solution

1. Step 1: Find matching case branch for sel = "10"

   The case statement has a branch when "10" => out_signal <= '0'; which matches the input.

2. Step 2: Determine assigned value

   For sel = "10", out_signal is assigned '0'.

3. Final Answer:

   '0' -> Option C

4. Quick Check:

   sel "10" sets out_signal to '0' [OK]

Hint: Match sel value to case branch to find output [OK]

Common Mistakes:

• Choosing default 'others' branch incorrectly
• Confusing '0' and '1' assignments
• Assuming syntax error without checking code

4. Identify the error in this VHDL process using a case statement:

process(sel)
begin
  case sel is
    when "00" => out_signal <= '0';
    when "01" => out_signal <= '1';
    when others => out_signal <= '0';
  end case;
end process;

medium

A. No error, code is correct

B. Missing semicolon after 'end case'

C. Missing 'when "10"' branch for sel

D. Incorrect use of 'others' keyword

Solution

1. Step 1: Check syntax and completeness

   The case statement covers "00", "01", and uses when others to cover all other values.

2. Step 2: Verify syntax correctness

   Semicolons and keywords are correctly placed; no syntax errors found.

3. Final Answer:

   No error, code is correct -> Option A

4. Quick Check:

   Proper use of 'others' covers missing cases [OK]

Hint: Use 'when others' to cover all missing cases [OK]

Common Mistakes:

• Thinking all cases must be listed explicitly
• Assuming missing branch causes error without 'others'
• Misplacing semicolons

5. You want to design a VHDL process that sets out_signal to '1' only when sel is "01" or "11", and '0' otherwise. Which case statement inside the process correctly implements this?

hard

A. case sel is
when "01" | "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

B. case sel is
when "01" => out_signal <= '1';
when "11" => out_signal <= '1';
when others => out_signal <= '0';
end case;

C. case sel is
when "01" => out_signal <= '1';
when others => out_signal <= '0';
end case;

D. case sel is
when "01" => out_signal <= '1';
when "10" => out_signal <= '1';
when others => out_signal <= '0';
end case;

Solution

1. Step 1: Identify required conditions

   Set out_signal to '1' only for sel = "01" or sel = "11", else '0'.

2. Step 2: Check each option for correctness

   case sel is when "01" | "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; uses invalid syntax with '|' for multiple choices in VHDL case. case sel is when "01" => out_signal <= '1'; when "11" => out_signal <= '1'; when others => out_signal <= '0'; end case; lists both cases separately, which is correct. case sel is when "01" => out_signal <= '1'; when others => out_signal <= '0'; end case; misses "11" case. case sel is when "01" => out_signal <= '1'; when "10" => out_signal <= '1'; when others => out_signal <= '0'; end case; incorrectly uses "10" instead of "11".

3. Final Answer:

   Option B with separate when clauses for "01" and "11" -> Option B

4. Quick Check:

   Separate when lines for each value = correct VHDL [OK]

Hint: List each case separately; no '|' for multiple values in VHDL [OK]

Common Mistakes:

• Using '|' to combine cases (invalid in VHDL)
• Missing one required case
• Confusing similar bit patterns