Mealy machine implementation in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the clock input in the entity.

VHDL

entity MealyMachine is
  Port (
    clk : [1];
    reset : in std_logic;
    input_signal : in std_logic;
    output_signal : out std_logic
  );
end MealyMachine;

Drag options to blanks, or click blank then click option'

Ain std_logic

Bbuffer std_logic

Cin integer

Dout std_logic

Attempts:

3 left

💡 Hint

Common Mistakes

Declaring clock as output or buffer.

Using integer type for clock.

The clock signal must be an input of type std_logic.

2fill in blank

medium

Complete the code to define the state type with two states S0 and S1.

VHDL

type state_type is ([1]);

Drag options to blanks, or click blank then click option'

AS0, S1

BIDLE, RUN

CSTART, STOP

DON, OFF

Attempts:

3 left

💡 Hint

Common Mistakes

Using unrelated state names like ON and OFF.

Forgetting commas between state names.

The Mealy machine uses states named S0 and S1.

3fill in blank

hard

Fix the error in the process sensitivity list to include the clock signal.

VHDL

process([1])
begin
  if rising_edge(clk) then
    -- state transitions
  end if;
end process;

Drag options to blanks, or click blank then click option'

Areset

Bclk

Cinput_signal

Doutput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Using reset instead of clk in sensitivity list.

Leaving sensitivity list empty.

The process must be sensitive to the clock signal clk to detect edges.

4fill in blank

hard

Fill both blanks to assign the next state and output based on input_signal.

VHDL

if input_signal = '1' then
  next_state <= [1];
  output_signal <= [2];
else
  next_state <= S0;
  output_signal <= '0';
end if;

Drag options to blanks, or click blank then click option'

AS1

B'1'

C'0'

DS0

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning output '0' when input is '1'.

Setting next_state to S0 incorrectly.

When input is '1', the machine moves to state S1 and output is '1'.

5fill in blank

hard

Fill all three blanks to complete the Mealy machine state transition and output logic.

VHDL

case current_state is
  when S0 =>
    if input_signal = '1' then
      next_state <= [1];
      output_signal <= [2];
    else
      next_state <= [3];
      output_signal <= '0';
    end if;
  when others =>
    next_state <= S0;
    output_signal <= '0';
end case;

Drag options to blanks, or click blank then click option'

AS1

B'1'

CS0

D'0'

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up next_state assignments.

Setting output to '0' incorrectly when input is '1'.

From state S0, if input is '1', go to S1 and output '1'. Otherwise, stay in S0 and output '0'.

Practice

1.

What is the key characteristic of a Mealy machine in VHDL?

Output depends on:

easy

A. Only next state

B. Only current state

C. Only previous input

D. Current state and current input

Solution

1. Step 1: Understand Mealy machine output logic

   Mealy machine outputs depend on both the current state and the current input signals.

2. Step 2: Compare with other machine types

   Unlike Moore machines, which depend only on the current state, Mealy machines also consider inputs for output.

3. Final Answer:

   Current state and current input -> Option D

4. Quick Check:

   Mealy output = state + input [OK]

Hint: Remember Mealy output changes immediately with input [OK]

Common Mistakes:

• Thinking output depends only on state
• Confusing Mealy with Moore machine
• Ignoring input signals in output logic

2.

Which VHDL code snippet correctly declares a Mealy machine state process sensitive to clock and reset?

process(_____)
begin
  if reset = '1' then
    state <= idle;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

easy

A. clk, reset

B. clk

C. reset

D. clk, input

Solution

1. Step 1: Identify signals controlling state updates

   The process must be sensitive to clock and asynchronous reset signals to update state properly.

2. Step 2: Confirm sensitivity list correctness

   Including both clk and reset ensures the process triggers on clock edges and reset changes.

3. Final Answer:

   clk, reset -> Option A

4. Quick Check:

   Sensitivity list = clk + reset [OK]

Hint: State process needs clock and reset sensitivity [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Including input signals unnecessarily
• Using only clock without reset

3.

Given this Mealy machine output process snippet, what is the output when state = S1 and input = '1'?

process(state, input)
begin
  case state is
    when S0 => output <= '0';
    when S1 =>
      if input = '1' then
        output <= '1';
      else
        output <= '0';
      end if;
    when others => output <= '0';
  end case;
end process;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Identify current state and input

   The state is S1 and input is '1'.

2. Step 2: Follow process logic for state S1

   For S1, if input is '1', output is assigned '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   State S1 + input '1' = output '1' [OK]

Hint: Check state and input conditions carefully [OK]

Common Mistakes:

• Ignoring input condition inside state
• Assuming output always '0'
• Confusing state names

4.

Identify the error in this Mealy machine next state process:

process(clk, reset)
begin
  if reset = '1' then
    state <= S0;
  elsif rising_edge(clk) then
    case state is
      when S0 => next_state <= S1;
      when S1 => next_state <= S2;
      when others => next_state <= S0;
    end case;
  end if;
end process;

medium

A. Missing input sensitivity in process

B. Assigning next_state inside clocked process

C. Using next_state instead of state for updates

D. No error, code is correct

Solution

1. Step 1: Understand state update logic

   The clocked process should update the current state, not next_state.

2. Step 2: Identify incorrect assignment

   Assigning next_state inside the clocked process is incorrect; state must be updated on clock edge.

3. Final Answer:

   Assigning next_state inside clocked process -> Option B

4. Quick Check:

   Clocked process updates state, not next_state [OK]

Hint: Update current state on clock, next_state in combinational [OK]

Common Mistakes:

• Updating next_state in clocked process
• Confusing state and next_state signals
• Ignoring reset signal

5.

You want to implement a Mealy machine in VHDL that outputs '1' only when the input sequence '101' is detected. Which approach correctly combines state and input for output logic?

hard

A. Use input only in sensitivity list; output depends only on input

B. Use only state in sensitivity list; output depends only on state

C. Use a process with state and input in sensitivity list; output depends on both current state and input

D. Use asynchronous reset to set output directly

Solution

1. Step 1: Understand Mealy machine output requirements

   Output depends on detecting input sequence and current state, so both must be considered.

2. Step 2: Implement output logic in process sensitive to state and input

   Including both in sensitivity list ensures output updates immediately when input or state changes.

3. Step 3: Confirm output depends on current state and input

   This matches Mealy machine behavior for sequence detection.

4. Final Answer:

   Use a process with state and input in sensitivity list; output depends on both current state and input -> Option C

5. Quick Check:

   Output = state + input for sequence detection [OK]

Hint: Output depends on state and input for sequence detection [OK]

Common Mistakes:

• Ignoring input in output logic
• Using Moore machine style output
• Relying only on asynchronous reset for output