If-then-else in process in VHDL

Introduction

If-then-else lets you choose what to do based on conditions inside a process. It helps your circuit make decisions step by step.

You want your circuit to do different things depending on input signals.

You need to check if a signal is high or low and act accordingly.

You want to create a simple decision-making block inside your design.

You want to set output signals based on multiple conditions.

Syntax

VHDL

process (sensitivity_list)
begin
  if condition then
    -- statements
  elsif another_condition then
    -- statements
  else
    -- statements
  end if;
end process;

The process block runs whenever signals in the sensitivity list change.

Use if, elsif, and else to check multiple conditions.

Examples

This sets y to '1' if a is '1', otherwise '0'.

VHDL

process (a, b)
begin
  if a = '1' then
    y <= '1';
  else
    y <= '0';
  end if;
end process;

This checks for a clock edge, then resets q or loads d depending on reset.

VHDL

process (clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

Sample Program

This VHDL code sets output y to '1' if a is '1'. If not, but b is '1', it sets y to '0'. Otherwise, y is set to high impedance 'Z'.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity simple_if is
  port (
    a : in std_logic;
    b : in std_logic;
    y : out std_logic
  );
end simple_if;

architecture behavior of simple_if is
begin
  process (a, b)
  begin
    if a = '1' then
      y <= '1';
    elsif b = '1' then
      y <= '0';
    else
      y <= 'Z'; -- high impedance
    end if;
  end process;
end behavior;

Important Notes

Always include end if; to close your if statement.

Conditions are checked in order; once one is true, the rest are skipped.

Use elsif for multiple conditions, not multiple if statements inside the same process.

Summary

If-then-else inside a process helps your circuit decide what to do based on signals.

Use if, elsif, and else to check conditions step by step.

Remember to list signals in the process sensitivity list so it runs when they change.

Practice

1. What is the main purpose of using if-then-else inside a VHDL process?

easy

A. To specify the clock frequency

B. To declare new signals

C. To choose different actions based on conditions

D. To define the entity interface

Solution

1. Step 1: Understand the role of if-then-else in VHDL process

   The if-then-else statement allows the process to select different actions depending on the condition evaluated.

2. Step 2: Compare other options

   Declaring signals, defining entity interface, and specifying clock frequency are unrelated to if-then-else usage inside a process.

3. Final Answer:

   To choose different actions based on conditions -> Option C

4. Quick Check:

   If-then-else controls actions by conditions [OK]

Hint: If-then-else picks actions based on conditions [OK]

Common Mistakes:

• Confusing if-then-else with signal declaration
• Thinking if-then-else defines entity ports
• Assuming it sets clock frequency

2. Which of the following is the correct syntax for an if-then-else statement inside a VHDL process?

easy

A. if (condition) { signal = '1'; } else { signal = '0'; }

B. if condition then signal <= '1'; else signal <= '0'; end if;

C. if condition: signal = '1' else signal = '0'

D. if condition then signal = 1 else signal = 0 end if

Solution

1. Step 1: Review VHDL if-then-else syntax

   VHDL uses 'if condition then ... else ... end if;' with signal assignment using '<=' and single quotes for bits.

2. Step 2: Check each option

   if condition then signal <= '1'; else signal <= '0'; end if; matches correct syntax. Options B and C use other languages' syntax. if condition then signal = 1 else signal = 0 end if misses semicolons and uses '=' instead of '<='.

3. Final Answer:

   if condition then signal <= '1'; else signal <= '0'; end if; -> Option B

4. Quick Check:

   VHDL if-then-else uses 'then', '<=', and 'end if;' [OK]

Hint: VHDL uses 'then', '<=', and ends with 'end if;' [OK]

Common Mistakes:

• Using curly braces or parentheses like other languages
• Using '=' instead of '<=' for signal assignment
• Omitting semicolons or 'end if;'

3. Consider the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    if input = '1' then
      output <= '0';
    else
      output <= '1';
    end if;
  end if;
end process;

What will be the value of output after a rising clock edge if input is '1'?

medium

A. '0'

B. Undefined

C. '1'

D. 'Z'

Solution

1. Step 1: Analyze the process on rising clock edge

   When clk rises, the process checks if input = '1'. If true, output is assigned '0'.

2. Step 2: Apply input value '1'

   Since input = '1', output <= '0' is executed.

3. Final Answer:

   '0' -> Option A

4. Quick Check:

   Input '1' sets output to '0' [OK]

Hint: Check condition inside rising_edge block carefully [OK]

Common Mistakes:

• Ignoring the nested if condition
• Confusing output with input value
• Assuming output stays unchanged

4. Identify the error in this VHDL process:

process(clk)
begin
  if clk'event and clk = '1' then
    if input = '1' then
      output <= '1'
    else
      output <= '0';
    end if;
  end if;
end process;

medium

A. Missing semicolon after output <= '1'

B. Wrong sensitivity list

C. Incorrect use of clk'event

D. Missing end if; for outer if

Solution

1. Step 1: Check each statement for syntax errors

   Inside the inner if, the line output <= '1' lacks a semicolon at the end.

2. Step 2: Verify other parts

   Sensitivity list includes clk, which is correct. clk'event and clk = '1' is valid for rising edge detection. The outer if has matching end if;.

3. Final Answer:

   Missing semicolon after output <= '1' -> Option A

4. Quick Check:

   Every statement must end with semicolon [OK]

Hint: Check semicolons after every assignment line [OK]

Common Mistakes:

• Forgetting semicolon after signal assignment
• Confusing clk'event with rising_edge(clk)
• Missing end if for if statements

5. You want to design a VHDL process that sets output to '1' if input1 is '1' and input2 is '0', otherwise sets output to '0'. Which is the correct if-then-else structure inside a clocked process?

hard

A. if rising_edge(clk) then
if input1 = '1' and input2 = '0' then
output <= '1'
else
output <= '0';
end if;
end if;

B. if rising_edge(clk) then
if input1 = '1' then
if input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

C. if rising_edge(clk) then
if input1 = '1' or input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

D. if rising_edge(clk) then
if input1 = '1' and input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

Solution

1. Step 1: Understand the condition

   Output should be '1' only if input1 = '1' AND input2 = '0'. Otherwise, output is '0'.

2. Step 2: Check each option's logic and syntax

   if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1'; else output <= '0'; end if; end if; correctly uses 'and' and proper if-then-else with semicolons. if rising_edge(clk) then if input1 = '1' then if input2 = '0' then output <= '1'; else output <= '0'; end if; end if; misses end if; for the rising_edge if. if rising_edge(clk) then if input1 = '1' or input2 = '0' then output <= '1'; else output <= '0'; end if; end if; uses 'or' instead of 'and'. if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1' else output <= '0'; end if; end if; misses semicolon after output <= '1'.

3. Final Answer:

   if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1'; else output <= '0'; end if; end if; -> Option D

4. Quick Check:

   Use 'and' for both conditions and end statements with semicolons [OK]

Hint: Use 'and' for both conditions and end lines with semicolons [OK]

Common Mistakes:

• Using 'or' instead of 'and' for conditions
• Missing semicolons after assignments
• Not closing nested if statements properly