Mealy machine implementation in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple Mealy machine process

Consider this VHDL process implementing a Mealy machine with one input x and output z. What is the output z after the input sequence x = 1, 0, 1 if the initial state is S0?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mealy_example is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           x : in STD_LOGIC;
           z : out STD_LOGIC);
end mealy_example;

architecture Behavioral of mealy_example is
    type state_type is (S0, S1);
    signal state, next_state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= S0;
        elsif rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    process(state, x)
    begin
        case state is
            when S0 =>
                if x = '1' then
                    next_state <= S1;
                    z <= '1';
                else
                    next_state <= S0;
                    z <= '0';
                end if;
            when S1 =>
                if x = '1' then
                    next_state <= S0;
                    z <= '0';
                else
                    next_state <= S1;
                    z <= '1';
                end if;
        end case;
    end process;
end Behavioral;

A z sequence: 1, 1, 1

B z sequence: 1, 1, 0

C z sequence: 0, 0, 1

D z sequence: 0, 1, 0

💡 Hint

Trace the state transitions and output for each input step starting from S0.

Starting at S0 with x=1, output z=1 and next state S1. Then at S1 with x=0, output z=1 and stay in S1. But the code sets z=1 only if x=0 in S1, so second output is 1. However, the question asks for the output after each input, so the sequence is z=1 (first input), z=1 (second input), then for x=1 at S1, output z=0 and next state S0. So the output sequence is 1, 1, 0. But the code assigns z in the combinational process, so the output corresponds to the current input and state. The correct sequence is 1, 1, 0 because after the first input, output is 1; second input 0 at S1 outputs 1; third input 1 at S1 outputs 0.

🧠 Conceptual

intermediate

Understanding Mealy machine output timing

In a Mealy machine implemented in VHDL, when is the output z updated relative to the clock edge?

A Output <code>z</code> updates immediately when inputs or state change (combinational logic).

B Output <code>z</code> updates only on the rising edge of the clock.

C Output <code>z</code> updates only on the falling edge of the clock.

D Output <code>z</code> updates randomly due to asynchronous behavior.

💡 Hint

Recall how Mealy machines produce outputs based on current state and inputs.

Mealy machine outputs depend on current state and inputs, so outputs are generated by combinational logic and update immediately when inputs or state change, not waiting for clock edges.

🔧 Debug

advanced

Identify the error in this Mealy machine VHDL code

What error will this VHDL code produce when compiled?

VHDL

architecture Behavioral of mealy_bug is
    type state_type is (IDLE, BUSY);
    signal state, next_state : state_type;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            state <= next_state;
        end if;
    end process;

    process(state, input_signal)
    begin
        case state is
            when IDLE =>
                if input_signal = '1' then
                    next_state <= BUSY;
                    output_signal <= '1';
                else
                    next_state <= IDLE;
                    output_signal <= '0';
                end if;
            when BUSY =>
                next_state <= IDLE;
                output_signal <= '1';
        end case;
    end process;
end Behavioral;

A Error: 'output_signal' is assigned in a process without being declared as a signal.

B Error: Missing sensitivity list for clocked process.

C Error: Multiple drivers for 'state' signal causing conflict.

D Error: 'next_state' assigned in combinational process but not initialized in all branches.

💡 Hint

Check if all possible paths assign 'next_state' in the combinational process.

The architecture declares 'state' and 'next_state', but 'output_signal' is not declared as a signal. Assigning to an undeclared identifier 'output_signal' (and similarly 'input_signal' and 'clk') will cause compilation errors, matching option A.

📝 Syntax

advanced

Identify the syntax error in this Mealy machine snippet

Which option correctly fixes the syntax error in this VHDL code snippet?

VHDL

process(state, x)
begin
    case state is
        when S0 =>
            if x = '1' then
                next_state <= S1
                z <= '1';
            else
                next_state <= S0;
                z <= '0';
            end if;
        when S1 =>
            next_state <= S0;
            z <= '0';
    end case;
end process;

A Replace 'case state is' with 'case state of'.

B Add 'end if;' after 'z <= '1';' line.

C Change 'when S0 =>' to 'when S0 then'.

D Add a semicolon after 'next_state <= S1' in the if branch.

💡 Hint

Check missing semicolons in VHDL statements.

VHDL requires semicolons after each signal assignment. The line 'next_state <= S1' is missing a semicolon, causing a syntax error.

🚀 Application

expert

Design a Mealy machine output for a sequence detector

You want to design a Mealy machine in VHDL that outputs '1' when the input sequence '101' is detected on input x. Which of these state transition and output assignments correctly implements this behavior?

A State S0: if x='1' next_state=S1, z='0'; S1: if x='0' next_state=S2, z='1'; S2: if x='1' next_state=S0, z='0'; else next_state=S0, z='0';

B State S0: if x='1' next_state=S1, z='1'; S1: if x='0' next_state=S2, z='0'; S2: if x='1' next_state=S0, z='0'; else next_state=S0, z='1';

C State S0: if x='1' next_state=S1, z='0'; S1: if x='0' next_state=S2, z='0'; S2: if x='1' next_state=S0, z='1'; else next_state=S0, z='0';

D State S0: if x='1' next_state=S1, z='0'; S1: if x='0' next_state=S2, z='0'; S2: if x='1' next_state=S0, z='0'; else next_state=S0, z='0';

💡 Hint

The output should be '1' only when the full sequence '101' is detected at the last input.

Option C correctly outputs '1' only when the sequence '101' is detected at state S2 with input '1'. Other options output '1' at wrong states or inputs.

Practice

1.

What is the key characteristic of a Mealy machine in VHDL?

Output depends on:

easy

A. Only next state

B. Only current state

C. Only previous input

D. Current state and current input

Solution

1. Step 1: Understand Mealy machine output logic

   Mealy machine outputs depend on both the current state and the current input signals.

2. Step 2: Compare with other machine types

   Unlike Moore machines, which depend only on the current state, Mealy machines also consider inputs for output.

3. Final Answer:

   Current state and current input -> Option D

4. Quick Check:

   Mealy output = state + input [OK]

Hint: Remember Mealy output changes immediately with input [OK]

Common Mistakes:

• Thinking output depends only on state
• Confusing Mealy with Moore machine
• Ignoring input signals in output logic

2.

Which VHDL code snippet correctly declares a Mealy machine state process sensitive to clock and reset?

process(_____)
begin
  if reset = '1' then
    state <= idle;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

easy

A. clk, reset

B. clk

C. reset

D. clk, input

Solution

1. Step 1: Identify signals controlling state updates

   The process must be sensitive to clock and asynchronous reset signals to update state properly.

2. Step 2: Confirm sensitivity list correctness

   Including both clk and reset ensures the process triggers on clock edges and reset changes.

3. Final Answer:

   clk, reset -> Option A

4. Quick Check:

   Sensitivity list = clk + reset [OK]

Hint: State process needs clock and reset sensitivity [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Including input signals unnecessarily
• Using only clock without reset

3.

Given this Mealy machine output process snippet, what is the output when state = S1 and input = '1'?

process(state, input)
begin
  case state is
    when S0 => output <= '0';
    when S1 =>
      if input = '1' then
        output <= '1';
      else
        output <= '0';
      end if;
    when others => output <= '0';
  end case;
end process;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Identify current state and input

   The state is S1 and input is '1'.

2. Step 2: Follow process logic for state S1

   For S1, if input is '1', output is assigned '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   State S1 + input '1' = output '1' [OK]

Hint: Check state and input conditions carefully [OK]

Common Mistakes:

• Ignoring input condition inside state
• Assuming output always '0'
• Confusing state names

4.

Identify the error in this Mealy machine next state process:

process(clk, reset)
begin
  if reset = '1' then
    state <= S0;
  elsif rising_edge(clk) then
    case state is
      when S0 => next_state <= S1;
      when S1 => next_state <= S2;
      when others => next_state <= S0;
    end case;
  end if;
end process;

medium

A. Missing input sensitivity in process

B. Assigning next_state inside clocked process

C. Using next_state instead of state for updates

D. No error, code is correct

Solution

1. Step 1: Understand state update logic

   The clocked process should update the current state, not next_state.

2. Step 2: Identify incorrect assignment

   Assigning next_state inside the clocked process is incorrect; state must be updated on clock edge.

3. Final Answer:

   Assigning next_state inside clocked process -> Option B

4. Quick Check:

   Clocked process updates state, not next_state [OK]

Hint: Update current state on clock, next_state in combinational [OK]

Common Mistakes:

• Updating next_state in clocked process
• Confusing state and next_state signals
• Ignoring reset signal

5.

You want to implement a Mealy machine in VHDL that outputs '1' only when the input sequence '101' is detected. Which approach correctly combines state and input for output logic?

hard

A. Use input only in sensitivity list; output depends only on input

B. Use only state in sensitivity list; output depends only on state

C. Use a process with state and input in sensitivity list; output depends on both current state and input

D. Use asynchronous reset to set output directly

Solution

1. Step 1: Understand Mealy machine output requirements

   Output depends on detecting input sequence and current state, so both must be considered.

2. Step 2: Implement output logic in process sensitive to state and input

   Including both in sensitivity list ensures output updates immediately when input or state changes.

3. Step 3: Confirm output depends on current state and input

   This matches Mealy machine behavior for sequence detection.

4. Final Answer:

   Use a process with state and input in sensitivity list; output depends on both current state and input -> Option C

5. Quick Check:

   Output = state + input for sequence detection [OK]

Hint: Output depends on state and input for sequence detection [OK]

Common Mistakes:

• Ignoring input in output logic
• Using Moore machine style output
• Relying only on asynchronous reset for output