Binary down counter in VHDL

Introduction

A binary down counter counts backwards in binary numbers. It helps track how many steps are left or how much time remains.

To count down seconds on a timer.

To track remaining items in a stock.

To create a countdown before an event starts.

To control loops that need to run a fixed number of times backwards.

Syntax

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity down_counter is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        count : out STD_LOGIC_VECTOR (3 downto 0)
    );
end down_counter;

architecture Behavioral of down_counter is
    signal counter_reg : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter_reg <= "1111"; -- start from 15
        elsif rising_edge(clk) then
            counter_reg <= counter_reg - 1;
        end if;
    end process;
    count <= counter_reg;
end Behavioral;

The counter counts down on each clock pulse.

Reset sets the counter back to the start value.

Examples

This line subtracts 1 from the current counter value on each clock.

VHDL

counter_reg <= counter_reg - 1;

This resets the counter to 15 when reset is active.

VHDL

if reset = '1' then
    counter_reg <= "1111"; -- reset to 15
end if;

Sample Program

This VHDL program creates a 4-bit binary down counter. It starts at 15 ("1111") and counts down by 1 on each clock pulse. When reset is high, it goes back to 15.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity down_counter is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        count : out STD_LOGIC_VECTOR (3 downto 0)
    );
end down_counter;

architecture Behavioral of down_counter is
    signal counter_reg : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter_reg <= "1111"; -- start from 15
        elsif rising_edge(clk) then
            counter_reg <= counter_reg - 1;
        end if;
    end process;
    count <= counter_reg;
end Behavioral;

Important Notes

VHDL counters often use signals and processes triggered by clock edges.

Make sure to handle reset to avoid unexpected counts.

Binary subtraction works naturally on std_logic_vector with the right libraries.

Summary

A binary down counter counts backwards in binary numbers.

It uses a clock signal to decrease the count step by step.

Reset sets the counter back to the starting number.

Practice

1.

What does a binary down counter do in VHDL?

easy

A. Generates random binary numbers continuously

B. Counts forwards in decimal numbers on each clock pulse

C. Counts backwards in binary numbers on each clock pulse

D. Stores a fixed binary value without changing

Solution

1. Step 1: Understand the function of a down counter

   A down counter decreases its count value by one on each clock pulse, moving backwards in binary.

2. Step 2: Compare options with definition

   Only Counts backwards in binary numbers on each clock pulse describes counting backwards in binary on clock pulses, matching the down counter behavior.

3. Final Answer:

   Counts backwards in binary numbers on each clock pulse -> Option C

4. Quick Check:

   Down counter = counts backwards [OK]

Hint: Down counter always decreases count on clock pulse [OK]

Common Mistakes:

• Confusing down counter with up counter
• Thinking it counts in decimal
• Assuming it holds a fixed value

2.

Which of the following is the correct VHDL syntax to declare a 4-bit binary down counter signal?

signal count : ?;

easy

A. std_logic_vector(3 downto 0)

B. integer range 0 to 15

C. bit_vector(0 to 3)

D. std_logic_vector(0 to 3)

Solution

1. Step 1: Identify correct vector type and direction

   For a 4-bit binary counter, std_logic_vector(3 downto 0) is standard to represent bits from MSB to LSB.

2. Step 2: Check other options for correctness

   The integer range uses integer, not vector; bit_vector with ascending range is less common; std_logic_vector(0 to 3) uses ascending range which is unusual for counters.

3. Final Answer:

   std_logic_vector(3 downto 0) -> Option A

4. Quick Check:

   4-bit vector uses std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of vector for bit signals
• Using ascending range instead of downto
• Confusing bit_vector with std_logic_vector

3.

Given this VHDL process for a 3-bit down counter starting at 7:

process(clk, reset)
begin
  if reset = '1' then
    count <= "111";
  elsif rising_edge(clk) then
    count <= count - 1;
  end if;
end process;

What is the value of count after 3 clock pulses (assuming reset is '0')?

medium

A. "101"

B. "100"

C. "011"

D. "110"

Solution

1. Step 1: Start from initial value after reset

   Reset sets count to "111" which is decimal 7.

2. Step 2: Subtract 1 on each clock pulse for 3 pulses

   7 - 1 = 6 ("110"), 6 - 1 = 5 ("101"), 5 - 1 = 4 ("100").

3. Final Answer:

   "100" -> Option B

4. Quick Check:

   7 - 3 = 4 = "100" [OK]

Hint: Subtract 1 per clock pulse from start value [OK]

Common Mistakes:

• Counting up instead of down
• Misinterpreting binary values
• Forgetting reset sets initial value

4.

Identify the error in this VHDL down counter process:

process(clk, reset)
begin
  if reset = '1' then
    count <= "1111";
  elsif clk'event and clk = '1' then
    count <= count + 1;
  end if;
end process;

medium

A. Reset value is incorrect for 4 bits

B. Missing signal declaration for count

C. Clock edge detection syntax is wrong

D. Counter counts up instead of down

Solution

1. Step 1: Analyze counting operation

   The process increments count with count + 1, which is counting up, not down.

2. Step 2: Verify other parts for errors

   Reset value "1111" is valid for 4 bits; clock edge detection syntax is correct; signal declaration is not shown but not necessarily an error here.

3. Final Answer:

   Counter counts up instead of down -> Option D

4. Quick Check:

   Down counter must decrement, not increment [OK]

Hint: Down counter subtracts 1, not adds 1 [OK]

Common Mistakes:

• Using count + 1 instead of count - 1
• Confusing clock edge syntax
• Ignoring reset value correctness

5.

You want to design a 5-bit binary down counter in VHDL that resets to 31 and stops counting when it reaches 0. Which approach correctly implements this behavior?

hard

A. Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count

B. Reset count to 0; on clock, count <= count - 1 unconditionally

C. Reset count to "00000"; on clock, if count < 31 then count <= count + 1

D. Reset count to "11111"; on clock, count <= count + 1 until 31

Solution

1. Step 1: Set initial count and stopping condition

   Reset to "11111" (decimal 31) is correct for 5 bits; stopping at 0 means counting down until zero.

2. Step 2: Implement conditional decrement

   On each clock, decrement only if count > 0; else hold count to stop at zero.

3. Final Answer:

   Reset count to "11111"; on clock, if count > 0 then count <= count - 1 else hold count -> Option A

4. Quick Check:

   Count down from 31 to 0, stop at 0 [OK]

Hint: Decrement only if count > 0 to stop at zero [OK]

Common Mistakes:

• Resetting to zero instead of max value
• Counting up instead of down
• Not stopping at zero, causing underflow