Variable vs signal inside process in VHDL

Introduction

Variables and signals are used to store values in VHDL, but they behave differently inside a process. Understanding this helps you write correct and predictable hardware descriptions.

When you want to store a temporary value that updates immediately inside a process.

When you want to communicate values between processes or outside a process.

When you need to model hardware behavior that depends on timing and delays.

When you want to avoid unexpected results caused by signal update delays.

When you want to optimize simulation speed by using variables inside processes.

Syntax

VHDL

process_name: process
  variable var_name : type := initial_value;
  begin
    var_name := new_value; -- variable updates immediately
    signal_name <= new_value; -- signal updates after process ends
end process process_name;

Variables are declared inside a process and update immediately when assigned.

Signals are declared outside processes and update only after the process suspends.

Examples

Variable count_var updates immediately inside the process on each clock edge.

VHDL

process(clk)
  variable count_var : integer := 0;
begin
  if rising_edge(clk) then
    count_var := count_var + 1; -- immediate update
  end if;
end process;

Signal count_sig updates only after the process finishes, so the new value is visible in the next simulation cycle.

VHDL

signal count_sig : integer := 0;
process(clk)
begin
  if rising_edge(clk) then
    count_sig <= count_sig + 1; -- signal update delayed
  end if;
end process;

Variable temp_var can be updated multiple times in the same process execution, using the latest value immediately.

VHDL

process(clk)
  variable temp_var : integer := 0;
begin
  if rising_edge(clk) then
    temp_var := 5;
    temp_var := temp_var + 2; -- uses updated value immediately
  end if;
end process;

Sample Program

This program shows a variable and a signal counting clock cycles. The variable updates immediately inside the process, so out_var shows the current count. The signal updates after the process ends, so out_sig shows the previous count value during the same clock cycle.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity var_vs_sig is
  port(
    clk : in std_logic;
    out_var : out integer;
    out_sig : out integer
  );
end var_vs_sig;

architecture behavior of var_vs_sig is
  signal sig_count : integer := 0;
begin
  process(clk)
    variable var_count : integer := 0;
  begin
    if rising_edge(clk) then
      var_count := var_count + 1; -- variable updates immediately
      sig_count <= sig_count + 1; -- signal updates after process ends
      out_var <= var_count;
      out_sig <= sig_count;
    end if;
  end process;
end behavior;

Important Notes

Variables inside a process behave like temporary storage that changes instantly.

Signals behave like wires that update their value after the process finishes.

Use variables for calculations inside a process and signals to communicate between processes or outside.

Summary

Variables update immediately inside a process; signals update after the process ends.

Variables are declared inside processes; signals are declared outside.

Use variables for temporary calculations and signals for communication.

Practice

1. In VHDL, inside a process, what is the main difference between a variable and a signal?

easy

A. Variables are visible outside the process; signals are local.

B. Signals update immediately; variables update after the process ends.

C. Variables update immediately; signals update after the process ends.

D. Signals use ':=' for assignment; variables use '<='.

Solution

1. Step 1: Understand variable update timing

   Variables inside a process update immediately when assigned using ':='.

2. Step 2: Understand signal update timing

   Signals update only after the process finishes, using '<=' assignment.

3. Final Answer:

   Variables update immediately; signals update after the process ends. -> Option C

4. Quick Check:

   Variable immediate update = A [OK]

Hint: Variables update instantly; signals wait until process ends [OK]

Common Mistakes:

• Confusing assignment operators ':=' and '<='
• Thinking signals update immediately inside process
• Assuming variables are visible outside the process

2. Which of the following is the correct way to assign a value to a variable inside a VHDL process?

easy

A. variable_var := '1';

B. signal_var <= '1';

C. variable_var <= '1';

D. signal_var := '1';

Solution

1. Step 1: Identify variable assignment syntax

   Variables inside a process use ':=' for assignment.

2. Step 2: Confirm correct option

   variable_var := '1'; uses ':=' with a variable, which is correct syntax.

3. Final Answer:

   variable_var := '1'; -> Option A

4. Quick Check:

   Variable assignment uses ':=' = B [OK]

Hint: Use ':=' for variables, '<=' for signals inside process [OK]

Common Mistakes:

• Using '<=' to assign variables
• Using ':=' to assign signals
• Mixing variable and signal names

3. Consider this VHDL process snippet:

process(clk)
begin
  if rising_edge(clk) then
    variable v : integer := 0;
    signal s : integer := 0;
    v := v + 1;
    s <= s + 1;
  end if;
end process;

What will be the value of v and s after the first clock rising edge?

medium

A. v = 0, s = 1

B. v = 1, s = 0

C. v = 1, s = 1

D. v = 0, s = 0

Solution

1. Step 1: Analyze variable update

   Variable v is initialized to 0 each clock, then incremented to 1 immediately.

2. Step 2: Analyze signal update

   Signal s is initialized to 0 each clock, but signal updates after process ends, so current value remains 0.

3. Final Answer:

   v = 1, s = 0 -> Option B

4. Quick Check:

   Variable immediate update, signal delayed update = C [OK]

Hint: Variables reset each run; signals update after process ends [OK]

Common Mistakes:

• Assuming signal updates immediately
• Forgetting variable re-initialization each clock
• Confusing variable and signal scopes

4. Identify the error in this VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    variable count : integer := 0;
    count <= count + 1;
  end if;
end process;

medium

A. Using '<=' to assign a variable inside process

B. Variable declared inside process

C. Missing signal declaration for count

D. No error, code is correct

Solution

1. Step 1: Check assignment operator for variable

   Variables must be assigned using ':=', not '<='.

2. Step 2: Confirm error

   Using '<=' on variable count causes syntax error.

3. Final Answer:

   Using '<=' to assign a variable inside process -> Option A

4. Quick Check:

   Variable assignment uses ':=' not '<=' = A [OK]

Hint: Variables use ':='; signals use '<=' inside process [OK]

Common Mistakes:

• Using '<=' for variables
• Thinking variables can't be declared inside process
• Confusing variable and signal declarations

5. You want to count the number of rising edges on a clock signal inside a process and use the count outside the process. Which is the correct approach?

hard

A. Use a variable to count inside the process and assign it to a signal after process ends.

B. Use a signal inside the process but assign it with ':='.

C. Use a variable only, since it updates immediately and is visible outside.

D. Use a signal to count inside the process with '<=' assignment.

Solution

1. Step 1: Understand visibility requirements

   Count must be visible outside process, so it must be a signal.

2. Step 2: Use correct assignment for signal

   Signals inside process are assigned with '<=' to update after process ends.

3. Final Answer:

   Use a signal to count inside the process with '<=' assignment. -> Option D

4. Quick Check:

   Signal visible outside, assigned with '<=' = D [OK]

Hint: Use signals for outside visibility; variables are local [OK]

Common Mistakes:

• Using variables expecting outside visibility
• Assigning signals with ':=' inside process
• Trying to assign variables outside process