Mealy machine implementation in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is a Mealy machine in digital design?

A Mealy machine is a type of finite state machine where the outputs depend on both the current state and the current inputs.

beginner

In VHDL, where are the outputs of a Mealy machine typically defined?

Outputs are usually defined inside the process that describes the state transitions, because they depend on both the current state and inputs.

intermediate

Why does a Mealy machine often react faster to inputs than a Moore machine?

Because Mealy machine outputs depend directly on inputs, they can change immediately when inputs change, without waiting for a state change.

beginner

What is the role of the clock signal in a Mealy machine VHDL implementation?

The clock signal synchronizes state changes, ensuring the machine updates its state only at clock edges.

beginner

How do you represent states in a Mealy machine VHDL code?

States are usually represented using an enumerated type, which makes the code clear and easy to read.

In a Mealy machine, the output depends on:

A Only current input

B Only current state

C Current state and current input

D Previous state

Mealy machine outputs depend on both the current state and the current input signals.

Which VHDL construct is commonly used to describe state transitions in a Mealy machine?

A Process with clock sensitivity

B Concurrent signal assignment

C Function outside process

D Package declaration

State transitions are described inside a process that is sensitive to the clock signal.

What type is best to define states in a Mealy machine in VHDL?

A Integer type

B Enumerated type

C Boolean type

D Real type

Enumerated types clearly represent states with meaningful names.

When do outputs in a Mealy machine update?

A Only on clock rising edge

B At power-up

C Only on reset

D Immediately when inputs or state change

Outputs depend on current inputs and state, so they update immediately when either changes.

Which statement about Mealy machines is true?

A Outputs can change asynchronously with inputs

B Outputs change only on clock edges

C Outputs depend only on state

D They have no outputs

Mealy machine outputs can change as soon as inputs change, asynchronously with respect to the clock.

Explain how a Mealy machine differs from a Moore machine in terms of output generation.

Think about when outputs update relative to inputs and states.

Describe the key components and structure of a Mealy machine implemented in VHDL.

Consider how states, inputs, outputs, and clock interact.

Practice

1.

What is the key characteristic of a Mealy machine in VHDL?

Output depends on:

easy

A. Only next state

B. Only current state

C. Only previous input

D. Current state and current input

Solution

1. Step 1: Understand Mealy machine output logic

   Mealy machine outputs depend on both the current state and the current input signals.

2. Step 2: Compare with other machine types

   Unlike Moore machines, which depend only on the current state, Mealy machines also consider inputs for output.

3. Final Answer:

   Current state and current input -> Option D

4. Quick Check:

   Mealy output = state + input [OK]

Hint: Remember Mealy output changes immediately with input [OK]

Common Mistakes:

• Thinking output depends only on state
• Confusing Mealy with Moore machine
• Ignoring input signals in output logic

2.

Which VHDL code snippet correctly declares a Mealy machine state process sensitive to clock and reset?

process(_____)
begin
  if reset = '1' then
    state <= idle;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

easy

A. clk, reset

B. clk

C. reset

D. clk, input

Solution

1. Step 1: Identify signals controlling state updates

   The process must be sensitive to clock and asynchronous reset signals to update state properly.

2. Step 2: Confirm sensitivity list correctness

   Including both clk and reset ensures the process triggers on clock edges and reset changes.

3. Final Answer:

   clk, reset -> Option A

4. Quick Check:

   Sensitivity list = clk + reset [OK]

Hint: State process needs clock and reset sensitivity [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Including input signals unnecessarily
• Using only clock without reset

3.

Given this Mealy machine output process snippet, what is the output when state = S1 and input = '1'?

process(state, input)
begin
  case state is
    when S0 => output <= '0';
    when S1 =>
      if input = '1' then
        output <= '1';
      else
        output <= '0';
      end if;
    when others => output <= '0';
  end case;
end process;

medium

A. '1'

B. '0'

C. Undefined

D. Error

Solution

1. Step 1: Identify current state and input

   The state is S1 and input is '1'.

2. Step 2: Follow process logic for state S1

   For S1, if input is '1', output is assigned '1'.

3. Final Answer:

   '1' -> Option A

4. Quick Check:

   State S1 + input '1' = output '1' [OK]

Hint: Check state and input conditions carefully [OK]

Common Mistakes:

• Ignoring input condition inside state
• Assuming output always '0'
• Confusing state names

4.

Identify the error in this Mealy machine next state process:

process(clk, reset)
begin
  if reset = '1' then
    state <= S0;
  elsif rising_edge(clk) then
    case state is
      when S0 => next_state <= S1;
      when S1 => next_state <= S2;
      when others => next_state <= S0;
    end case;
  end if;
end process;

medium

A. Missing input sensitivity in process

B. Assigning next_state inside clocked process

C. Using next_state instead of state for updates

D. No error, code is correct

Solution

1. Step 1: Understand state update logic

   The clocked process should update the current state, not next_state.

2. Step 2: Identify incorrect assignment

   Assigning next_state inside the clocked process is incorrect; state must be updated on clock edge.

3. Final Answer:

   Assigning next_state inside clocked process -> Option B

4. Quick Check:

   Clocked process updates state, not next_state [OK]

Hint: Update current state on clock, next_state in combinational [OK]

Common Mistakes:

• Updating next_state in clocked process
• Confusing state and next_state signals
• Ignoring reset signal

5.

You want to implement a Mealy machine in VHDL that outputs '1' only when the input sequence '101' is detected. Which approach correctly combines state and input for output logic?

hard

A. Use input only in sensitivity list; output depends only on input

B. Use only state in sensitivity list; output depends only on state

C. Use a process with state and input in sensitivity list; output depends on both current state and input

D. Use asynchronous reset to set output directly

Solution

1. Step 1: Understand Mealy machine output requirements

   Output depends on detecting input sequence and current state, so both must be considered.

2. Step 2: Implement output logic in process sensitive to state and input

   Including both in sensitivity list ensures output updates immediately when input or state changes.

3. Step 3: Confirm output depends on current state and input

   This matches Mealy machine behavior for sequence detection.

4. Final Answer:

   Use a process with state and input in sensitivity list; output depends on both current state and input -> Option C

5. Quick Check:

   Output = state + input for sequence detection [OK]

Hint: Output depends on state and input for sequence detection [OK]

Common Mistakes:

• Ignoring input in output logic
• Using Moore machine style output
• Relying only on asynchronous reset for output