Relational operators in VHDL - Mini Project: Build & Apply

Relational Operators in VHDL

📖 Scenario: You are designing a simple VHDL module to compare two 4-bit input signals. This is a common task in digital circuits where decisions are made based on comparisons.

🎯 Goal: Build a VHDL process that uses relational operators to compare two 4-bit inputs and sets output signals accordingly.

📋 What You'll Learn

Create two 4-bit std_logic_vector inputs named A and B

Create output signals equal, greater, and less of type std_logic

Use relational operators =, >, and < to compare A and B

Assign the results of comparisons to the output signals inside a process

💡 Why This Matters

🌍 Real World

Comparators are used in digital circuits to make decisions, such as sorting, selecting maximum values, or triggering events based on signal comparisons.

💼 Career

Understanding relational operators in VHDL is essential for hardware design engineers working on FPGA or ASIC projects where conditional logic is required.

1

DATA SETUP: Declare inputs and outputs

Declare two 4-bit std_logic_vector inputs named A and B, and three std_logic outputs named equal, greater, and less inside an entity called Comparator.

VHDL

entity Comparator is
    Port (
        -- Declare inputs and outputs here
    );
end Comparator;

Hint

Use std_logic_vector(3 downto 0) for 4-bit inputs and std_logic for outputs.

2

CONFIGURATION: Create architecture and signals

Create an architecture named Behavioral for the Comparator entity and declare a process sensitive to A and B.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        equal : out std_logic;
        greater : out std_logic;
        less : out std_logic
    );
end Comparator;

architecture Behavioral of Comparator is
begin
    process(A, B)
    begin
        -- Your code here
    end process;
end Behavioral;

Hint

Use process(A, B) to react to changes in inputs.

3

CORE LOGIC: Use relational operators to compare inputs

Inside the process, use relational operators =, >, and < to compare A and B. Assign '1' to equal if A = B, to greater if A > B, and to less if A < B. Assign '0' to the other outputs accordingly.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        equal : out std_logic;
        greater : out std_logic;
        less : out std_logic
    );
end Comparator;

architecture Behavioral of Comparator is
begin
    process(A, B)
    begin
        -- Use relational operators to compare A and B
        -- Your code here
    end process;
end Behavioral;

Hint

Use if, elsif, and else with relational operators to set outputs.

4

OUTPUT: Test and observe the output signals

Write a simple testbench process that assigns values to A and B and prints the values of equal, greater, and less signals using report statements.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator_tb is
end Comparator_tb;

architecture Behavioral of Comparator_tb is
    signal A : std_logic_vector(3 downto 0) := "0000";
    signal B : std_logic_vector(3 downto 0) := "0000";
    signal equal, greater, less : std_logic;
begin
    uut: entity work.Comparator
        port map(
            A => A,
            B => B,
            equal => equal,
            greater => greater,
            less => less
        );

    process
    begin
        -- Your code here
    end process;
end Behavioral;

Hint

Use report statements to print signal values after assigning test values to A and B.

Practice

1. Which of the following is a valid relational operator in VHDL to check if two values are equal?

easy

A. ===

B. ==

C. =

D. equals

Solution

1. Step 1: Identify equality operator in VHDL

   In VHDL, the equality operator to compare two values is a single equals sign =.

2. Step 2: Compare with other options

   Options A and B use double or triple equals which are not valid in VHDL. equals is a word, not an operator.

3. Final Answer:

   = -> Option C

4. Quick Check:

   Equality operator in VHDL: = [OK]

Hint: Remember: VHDL uses single '=' for equality check [OK]

Common Mistakes:

• Using '==' or '===' instead of '='
• Confusing with other language syntax
• Using words like 'equals' instead of operators

2. Which of the following is the correct syntax to check if signal a is less than or equal to signal b in VHDL?

easy

A. if a <= b then

B. if a =< b then

C. if a => b then

D. if a <== b then

Solution

1. Step 1: Recall the correct relational operator for less than or equal

   The correct operator is <= in VHDL.

2. Step 2: Check syntax of the if statement

   The correct syntax is if a <= b then. Other options have invalid operator sequences.

3. Final Answer:

   if a <= b then -> Option A

4. Quick Check:

   Less than or equal operator = <= [OK]

Hint: Use <= for less or equal, not =< or => [OK]

Common Mistakes:

• Swapping operator symbols like =< or =>
• Using double or triple symbols incorrectly
• Misplacing operators in if statements

3. Given the following VHDL code snippet, what is the value of result after execution?

signal a : integer := 5;
signal b : integer := 10;
signal result : boolean;

result <= (a > b);

medium

A. FALSE

B. TRUE

C. Undefined

D. Syntax Error

Solution

1. Step 1: Evaluate the relational expression (a > b)

   Since a = 5 and b = 10, 5 > 10 is FALSE.

2. Step 2: Assign the result signal

   The boolean signal result will be assigned FALSE.

3. Final Answer:

   FALSE -> Option A

4. Quick Check:

   5 > 10 = FALSE [OK]

Hint: Compare values directly; 5 > 10 is false [OK]

Common Mistakes:

• Assuming 5 > 10 is true
• Confusing signal assignment with variable assignment
• Thinking result is undefined without initialization

4. Identify the error in the following VHDL code snippet:

signal x : integer := 7;
signal y : integer := 3;
signal flag : boolean;

flag <= (x <> y);

medium

A. No error, code is correct

B. Missing semicolon after signal declarations

C. Incorrect operator for inequality, should be '!='

D. Operator '<>' is invalid for inequality

Solution

1. Step 1: Check the inequality operator in VHDL

   In VHDL, the operator for inequality is /=, not <>.

2. Step 2: Verify the code snippet

   The code uses <> which is not valid in VHDL. Operator '<>' is invalid for inequality correctly identifies this error.

3. Final Answer:

   Operator '<>' is invalid for inequality -> Option D

4. Quick Check:

   Inequality operator in VHDL = /= [OK]

Hint: Use '/=' for not equal, not '<>' [OK]

Common Mistakes:

• Using '<>' from other languages instead of '/='
• Ignoring syntax errors in operators
• Assuming no error when operator is wrong

5. You want to write a VHDL condition that checks if signal temp is between 10 and 20 inclusive. Which expression correctly uses relational operators to do this?

hard

A. if 10 <= temp <= 20 then

B. if (temp >= 10) and (temp <= 20) then

C. if (temp > 10) and (temp < 20) then

D. if temp in 10 to 20 then

Solution

1. Step 1: Understand range checking in VHDL

   VHDL does not support chained comparisons like 10 <= temp <= 20. Instead, use logical AND to combine two comparisons.

2. Step 2: Check each option

   if (temp >= 10) and (temp <= 20) then correctly uses (temp >= 10) and (temp <= 20). if 10 <= temp <= 20 then is invalid syntax. if (temp > 10) and (temp < 20) then excludes 10 and 20 by using strict inequalities. if temp in 10 to 20 then uses 'in' which is not valid for integer range checks.

3. Final Answer:

   if (temp >= 10) and (temp <= 20) then -> Option B

4. Quick Check:

   Use AND to combine two relational checks [OK]

Hint: Combine two comparisons with AND for range checks [OK]

Common Mistakes:

• Using chained comparisons like 10 <= temp <= 20
• Using strict inequalities when inclusive needed
• Using 'in' keyword incorrectly for integers