Relational operators in VHDL - Mini Project: Build & Apply

Relational Operators in VHDL

📖 Scenario: You are designing a simple VHDL module to compare two 4-bit input signals. This is a common task in digital circuits where decisions are made based on comparisons.

🎯 Goal: Build a VHDL process that uses relational operators to compare two 4-bit inputs and sets output signals accordingly.

📋 What You'll Learn

Create two 4-bit std_logic_vector inputs named A and B

Create output signals equal, greater, and less of type std_logic

Use relational operators =, >, and < to compare A and B

Assign the results of comparisons to the output signals inside a process

💡 Why This Matters

🌍 Real World

Comparators are used in digital circuits to make decisions, such as sorting, selecting maximum values, or triggering events based on signal comparisons.

💼 Career

Understanding relational operators in VHDL is essential for hardware design engineers working on FPGA or ASIC projects where conditional logic is required.

1

DATA SETUP: Declare inputs and outputs

Declare two 4-bit std_logic_vector inputs named A and B, and three std_logic outputs named equal, greater, and less inside an entity called Comparator.

VHDL

entity Comparator is
    Port (
        -- Declare inputs and outputs here
    );
end Comparator;

Need a hint?

Use std_logic_vector(3 downto 0) for 4-bit inputs and std_logic for outputs.

2

CONFIGURATION: Create architecture and signals

Create an architecture named Behavioral for the Comparator entity and declare a process sensitive to A and B.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        equal : out std_logic;
        greater : out std_logic;
        less : out std_logic
    );
end Comparator;

architecture Behavioral of Comparator is
begin
    process(A, B)
    begin
        -- Your code here
    end process;
end Behavioral;

Need a hint?

Use process(A, B) to react to changes in inputs.

3

CORE LOGIC: Use relational operators to compare inputs

Inside the process, use relational operators =, >, and < to compare A and B. Assign '1' to equal if A = B, to greater if A > B, and to less if A < B. Assign '0' to the other outputs accordingly.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator is
    Port (
        A : in std_logic_vector(3 downto 0);
        B : in std_logic_vector(3 downto 0);
        equal : out std_logic;
        greater : out std_logic;
        less : out std_logic
    );
end Comparator;

architecture Behavioral of Comparator is
begin
    process(A, B)
    begin
        -- Use relational operators to compare A and B
        -- Your code here
    end process;
end Behavioral;

Need a hint?

Use if, elsif, and else with relational operators to set outputs.

4

OUTPUT: Test and observe the output signals

Write a simple testbench process that assigns values to A and B and prints the values of equal, greater, and less signals using report statements.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Comparator_tb is
end Comparator_tb;

architecture Behavioral of Comparator_tb is
    signal A : std_logic_vector(3 downto 0) := "0000";
    signal B : std_logic_vector(3 downto 0) := "0000";
    signal equal, greater, less : std_logic;
begin
    uut: entity work.Comparator
        port map(
            A => A,
            B => B,
            equal => equal,
            greater => greater,
            less => less
        );

    process
    begin
        -- Your code here
    end process;
end Behavioral;

Need a hint?

Use report statements to print signal values after assigning test values to A and B.