Relational operators in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of relational operator in VHDL

What is the output of this VHDL process when a = 5 and b = 3?

VHDL

process(a, b)
begin
  if a > b then
    report "a is greater";
  else
    report "b is greater or equal";
  end if;
end process;

A b is greater or equal

B a is greater

C No output

D Compilation error

💡 Hint

Compare the values of a and b using the > operator.

Since 5 > 3 is true, the process reports "a is greater".

❓ Predict Output

intermediate

Relational operator with std_logic_vector

What is the result of the comparison "1010" > "1001" in VHDL?

VHDL

signal a, b : std_logic_vector(3 downto 0);
begin
a <= "1010";
b <= "1001";
process(a, b)
begin
if a > b then
  report "a is greater";
else
  report "b is greater or equal";
end if;
end process;

A Compilation error due to type mismatch

B b is greater or equal

C No output

D a is greater

💡 Hint

Relational operators like > are directly supported on std_logic_vector (in std_logic_1164), comparing bit-by-bit from MSB to LSB.

Relational operators are not directly defined for std_logic_vector in standard packages; comparing std_logic_vector with > causes a compilation error due to type mismatch.

🔧 Debug

advanced

Identify the error in relational operator usage

What error does this VHDL code produce?

VHDL

signal x : integer := 10;
signal y : integer := 20;
begin
process(x, y)
begin
if x =< y then
  report "x is less or equal to y";
end if;
end process;

A No error, outputs "x is less or equal to y"

B Runtime error: comparison failed

C Syntax error: invalid operator =<

D Type error: incompatible types

💡 Hint

Check the spelling of the less or equal operator.

The correct operator is <=, not =<.

❓ Predict Output

advanced

Output of combined relational expressions

What is the output of this VHDL code snippet?

VHDL

signal a, b, c : integer := 5;
begin
process(a, b, c)
begin
if (a < b) or (b = c) then
  report "Condition true";
else
  report "Condition false";
end if;
end process;

A Condition true

B Condition false

C Compilation error due to operator precedence

D No output

💡 Hint

Evaluate each relational expression separately and then combine with or.

a < b is false (5 < 5 is false), b = c is true (5 = 5), so overall true.

🧠 Conceptual

expert

Relational operator behavior with signed types

In VHDL, given signal s1, s2 : signed(3 downto 0); with s1 = "1001" and s2 = "0111", what is the result of s1 < s2?

A False, because both are treated as unsigned

B False, because "1001" is 9 and "0111" is 7

C Compilation error: relational operators not defined for signed

D True, because "1001" is -7 and "0111" is 7

💡 Hint

Remember how signed numbers are represented in VHDL.

The signed type interprets "1001" as -7 and "0111" as 7, so s1 < s2 is true.