Concept Flow - Logical operators (and, or, xor, not, nand, nor)
Input A, Input B
Output Result
Use in Circuit or Simulation
Logical operators take two inputs (except not) and produce an output based on the operator's rule.
library ieee; use ieee.std_logic_1164.all; signal A, B, Result_and, Result_or : std_logic; Result_and <= A and B; Result_or <= A or B;
| Step | A | B | A and B | A or B | A xor B | not A | A nand B | A nor B |
|---|---|---|---|---|---|---|---|---|
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| 2 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |
| 3 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 4 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| Exit | - | - | - | - | - | - | - | All input combinations tested |
| Variable | Start | After 1 | After 2 | After 3 | After 4 | Final |
|---|---|---|---|---|---|---|
| A | - | 0 | 0 | 1 | 1 | 1 |
| B | - | 0 | 1 | 0 | 1 | 1 |
| A and B | - | 0 | 0 | 0 | 1 | 1 |
| A or B | - | 0 | 1 | 1 | 1 | 1 |
| A xor B | - | 0 | 1 | 1 | 0 | 0 |
| not A | - | 1 | 1 | 0 | 0 | 0 |
| A nand B | - | 1 | 1 | 1 | 0 | 0 |
| A nor B | - | 1 | 0 | 0 | 0 | 0 |
Logical operators in VHDL: - and, or, xor: binary operators on two inputs - not: unary operator on one input - nand, nor: inverse of and, or - Outputs are std_logic values (0 or 1) - Used to build digital logic circuits