Logical operators (and, or, xor, not, nand, nor) in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of simple AND and OR operations

What is the output of the following VHDL process when A = '1' and B = '0'?

VHDL

process(A, B) is
  variable result_and : std_logic;
  variable result_or : std_logic;
begin
  result_and := A and B;
  result_or := A or B;
  report "AND result: " & std_logic'image(result_and);
  report "OR result: " & std_logic'image(result_or);
end process;

A AND result: '0', OR result: '1'

B AND result: '1', OR result: '0'

C AND result: '1', OR result: '1'

D AND result: '0', OR result: '0'

💡 Hint

Remember that AND requires both inputs to be '1' to output '1'. OR outputs '1' if any input is '1'.

AND of '1' and '0' is '0'. OR of '1' and '0' is '1'.

❓ Predict Output

intermediate

XOR and NOT operator output

Given signals A = '1' and B = '1', what will be the output of the following VHDL code?

VHDL

process(A, B) is
  variable result_xor : std_logic;
  variable result_not : std_logic;
begin
  result_xor := A xor B;
  result_not := not A;
  report "XOR result: " & std_logic'image(result_xor);
  report "NOT result: " & std_logic'image(result_not);
end process;

A XOR result: '1', NOT result: '1'

B XOR result: '1', NOT result: '0'

C XOR result: '0', NOT result: '1'

D XOR result: '0', NOT result: '0'

💡 Hint

XOR outputs '1' only if inputs differ. NOT flips the input bit.

XOR of '1' and '1' is '0'. NOT of '1' is '0'.

❓ Predict Output

advanced

NAND and NOR operator results

What will be the output of this VHDL process if A = '0' and B = '0'?

VHDL

process(A, B) is
  variable result_nand : std_logic;
  variable result_nor : std_logic;
begin
  result_nand := A nand B;
  result_nor := A nor B;
  report "NAND result: " & std_logic'image(result_nand);
  report "NOR result: " & std_logic'image(result_nor);
end process;

A NAND result: '1', NOR result: '0'

B NAND result: '0', NOR result: '0'

C NAND result: '0', NOR result: '1'

D NAND result: '1', NOR result: '1'

💡 Hint

NAND is the inverse of AND, NOR is the inverse of OR.

AND of '0' and '0' is '0', so NAND is '1'. OR of '0' and '0' is '0', so NOR is '1'.

🔧 Debug

advanced

Identify the error in this VHDL logical expression

What error will this VHDL code produce?

VHDL

signal A, B : std_logic;
signal result : std_logic;
begin
  result <= A and or B;

A Type error: incompatible types for 'and' operator

B Syntax error: unexpected 'or' after 'and'

C Runtime error: signal assignment conflict

D No error, code runs correctly

💡 Hint

Check the operator sequence carefully.

The expression 'A and or B' is invalid syntax because 'and' and 'or' cannot be used consecutively without operands.

🧠 Conceptual

expert

Logical operator behavior with 'U' (uninitialized) signals

In VHDL, if signal A = 'U' (uninitialized) and B = '1', what is the result of A nand B?

A 'U' because NAND with uninitialized input propagates unknown

B '1' because NAND outputs '1' if any input is '0' or unknown

C '0' because NAND inverts AND and AND with 'U' and '1' is '0'

D 'X' because VHDL uses 'X' for unknown logic states

💡 Hint

Consider how VHDL handles unknown ('U') logic values in logical operations.

In VHDL, logical operations with 'U' propagate 'U' because the value is unknown, so NAND with 'U' and '1' results in 'U'.