Clock generation process in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a clock signal in VHDL.

VHDL

signal clk : std_logic := '[1]';

Drag options to blanks, or click blank then click option'

A'1'

B'0'

C"0"

D"1"

Attempts:

3 left

💡 Hint

Common Mistakes

Using double quotes instead of single quotes for std_logic.

Initializing clock to '1' instead of '0'.

The clock signal is usually initialized to '0' as a std_logic value.

2fill in blank

medium

Complete the code to create a clock generation process with a 10 ns period.

VHDL

process
begin
  clk <= not clk;
  wait for [1];
end process;

Drag options to blanks, or click blank then click option'

A1 ns

B10 ns

C20 ns

D5 ns

Attempts:

3 left

💡 Hint

Common Mistakes

Using the full period instead of half period in wait statement.

Using incorrect time units.

The clock toggles every half period, so for a 10 ns period, wait for 5 ns.

3fill in blank

hard

Fix the error in the clock generation process to avoid simulation issues.

VHDL

process
begin
  [1] <= not clk;
  wait for 5 ns;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Bclk <= clk

Cclk = not clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using '=' instead of '<=' for signal assignment.

Assigning the signal to itself without toggling.

The signal assignment must be 'clk <= not clk;' to toggle the clock correctly.

4fill in blank

hard

Fill both blanks to create a clock process with a 50 MHz frequency.

VHDL

process
begin
  clk <= not clk;
  wait for [1];
  wait for [2];
end process;

Drag options to blanks, or click blank then click option'

A10 ns

B5 ns

C20 ns

D25 ns

Attempts:

3 left

💡 Hint

Common Mistakes

Using full period instead of half period.

Using different wait times causing incorrect clock frequency.

For 50 MHz, period is 20 ns, so half period is 10 ns. The process should wait for half period once, not twice. But here two waits are given, so both should be 5 ns to total 10 ns.

5fill in blank

hard

Fill all three blanks to complete a clock generation process with a 100 MHz clock.

VHDL

process
begin
  [1] <= not [2];
  wait for [3];
end process;

Drag options to blanks, or click blank then click option'

Aclk

C5 ns

D10 ns

Attempts:

3 left

💡 Hint

Common Mistakes

Using different signal names for assignment and toggling.

Using full period wait instead of half period.

The clock signal 'clk' toggles by assigning 'clk <= not clk;' and waits for half period 5 ns for 100 MHz.