Clock generation process in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output waveform frequency?

Given the following VHDL clock generation process, what is the frequency of the output clock signal clk_out if the input clock clk_in is 50 MHz?

VHDL

process(clk_in)
begin
  if rising_edge(clk_in) then
    clk_out <= not clk_out;
  end if;
end process;

A 25 MHz

B 50 MHz

C 100 MHz

D 12.5 MHz

💡 Hint

Think about how many input clock cycles it takes for clk_out to complete one full cycle.

The process toggles clk_out on every rising edge of clk_in. So clk_out changes state every input clock cycle, meaning its period is twice the input clock period. Therefore, the frequency is half of 50 MHz, which is 25 MHz.

🧠 Conceptual

intermediate

Why use a clock generation process in VHDL?

What is the main purpose of a clock generation process in VHDL designs?

A To generate random numbers for testing

B To create a slower or derived clock signal from a faster input clock

C To reset all flip-flops asynchronously

D To convert analog signals to digital

💡 Hint

Think about how hardware designs often need clocks at different speeds.

Clock generation processes are used to produce new clock signals at different frequencies or phases derived from an existing clock. This helps in timing control for different parts of a design.

🔧 Debug

advanced

Identify the error in this clock generation process

What error will this VHDL clock generation process cause when synthesized?

VHDL

process(clk_in)
begin
  if clk_in = '1' then
    clk_out <= not clk_out;
  end if;
end process;

A Synthesis will fail due to missing sensitivity list

B No error, the code works correctly

C clk_out will never toggle because rising_edge is missing

D clk_out will toggle asynchronously causing glitches

💡 Hint

Consider the difference between checking clk_in = '1' and using rising_edge(clk_in).

Checking clk_in = '1' triggers the process whenever clk_in is high, not just on the rising edge. This can cause multiple toggles and glitches. The correct approach is to use if rising_edge(clk_in).

📝 Syntax

advanced

Which option correctly implements a clock divider by 8?

Choose the VHDL process that correctly divides the input clock frequency by 8.

A

process(clk_in)
variable count : integer range 0 to 3 := 0;
begin
  if rising_edge(clk_in) then
    if count = 3 then
      clk_out <= not clk_out;
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

B

process(clk_in)
begin
  if rising_edge(clk_in) then
    clk_out <= not clk_out;
  end if;
end process;

C

process(clk_in)
variable count : integer range 0 to 4 := 0;
begin
  if rising_edge(clk_in) then
    if count = 4 then
      clk_out <= not clk_out;
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

D

process(clk_in)
variable count : integer range 0 to 2 := 0;
begin
  if rising_edge(clk_in) then
    if count = 2 then
      clk_out <= not clk_out;
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

💡 Hint

Think about how many input clock cycles are needed to toggle the output clock to get a divide by 8.

To divide by 8, the output clock must toggle every 4 input clock cycles. Option A counts from 0 to 3 (4 cycles) before toggling clk_out. Other options count incorrectly or toggle every cycle.

🚀 Application

expert

Calculate the output clock frequency for a complex clock generation process

Consider this VHDL clock generation process:

process(clk_in)
variable count : integer range 0 to 9 := 0;
begin
  if rising_edge(clk_in) then
    if count = 9 then
      clk_out <= not clk_out;
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

If clk_in is 100 MHz, what is the frequency of clk_out?

A 50 MHz

B 10 MHz

C 5 MHz

D 100 MHz

💡 Hint

Calculate how many input clock cycles make one full cycle of clk_out.

The counter counts from 0 to 9 (10 cycles) before toggling clk_out. One full cycle of clk_out requires two toggles, so 20 input clock cycles. At 100 MHz input clock, output frequency is 100 MHz / 20 = 5 MHz.