Watchdog timer design in VHDL - Step-by-Step Execution

Concept Flow - Watchdog timer design

Start

↓

Reset Watchdog Counter

↓

Count Clock Cycles

↓

Check if Counter >= Timeout

↓

Wait for Reset

The watchdog timer resets a counter on a reset signal, counts clock cycles, and triggers a reset if the count reaches a timeout.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    counter <= 0;
    reset_out <= '0';
  elsif rising_edge(clk) then
    if counter < TIMEOUT then
      counter <= counter + 1;
      if counter = TIMEOUT - 1 then
        reset_out <= '1';
      end if;
    else
      reset_out <= '1';
    end if;
  end if;
end process;

This VHDL process resets the counter on reset, increments it each clock cycle, and triggers reset_out when timeout is reached.

Execution Table

Step	reset	clk rising_edge	counter before	counter after	Condition (counter < TIMEOUT)	Action	reset_out
1	1	No	X	0	N/A	Reset counter to 0	'0'
2	0	Yes	0	1	True	Increment counter	'0'
3	0	Yes	1	2	True	Increment counter	'0'
4	0	Yes	2	3	True	Increment counter	'0'
5	0	Yes	3	4	True	Increment counter	'0'
6	0	Yes	4	5	True	Increment counter and trigger reset_out	'1'
7	0	Yes	5	5	False	Keep reset_out '1'	'1'
8	1	No	5	0	N/A	Reset counter to 0	'0'

💡 Process continues indefinitely; reset_out triggers when counter reaches TIMEOUT.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8
counter	X	0	1	2	3	4	5	5	0
reset_out	'0'	'0'	'0'	'0'	'0'	'0'	'1'	'1'	'0'

Key Moments - 3 Insights

Why does the counter reset to 0 when reset = '1' even if clk is not rising?

Because the process is sensitive to reset, the reset condition is checked first and resets the counter immediately (see Step 1 and Step 8 in execution_table).

Why does reset_out stay '1' after the counter reaches TIMEOUT?

Once the counter reaches TIMEOUT, reset_out is set to '1' and remains '1' until reset is asserted again (see Steps 6 and 7).

Why doesn't the counter increment after reaching TIMEOUT?

The condition counter < TIMEOUT becomes false, so the counter stops incrementing and holds its value (see Steps 6 and 7).

Visual Quiz - 3 Questions

Look at the execution_table at Step 5. What is the value of counter after the clock rising edge?

A 3

B 5

C 4

D 2

💡 Hint

Check the 'counter after' column at Step 5 in the execution_table.

At which step does reset_out first become '1' according to the execution_table?

A Step 6

B Step 5

C Step 4

D Step 7

💡 Hint

Look at the 'reset_out' column and find when it changes to '1'.

If reset is asserted at Step 8, what happens to the counter value?

A It stays at 5

B It resets to 0

C It increments by 1

D It becomes undefined

💡 Hint

See Step 8 in execution_table where reset = '1' causes counter to reset.

Concept Snapshot

Watchdog Timer in VHDL:
- Reset counter on reset signal
- Increment counter each clock rising edge
- If counter < TIMEOUT, keep counting
- If counter >= TIMEOUT, trigger reset_out
- reset_out stays active until reset
- Ensures system reset if no reset signal within timeout

Full Transcript

This VHDL watchdog timer design resets a counter when the reset signal is high. On each rising clock edge, if the counter is less than the TIMEOUT value, it increments. When the counter reaches the TIMEOUT, it triggers a reset output signal. This reset_out signal remains active until the reset signal is asserted again, which resets the counter and clears reset_out. The process ensures the system resets if it does not receive a reset signal within the timeout period.

Practice

1. What is the main purpose of a watchdog timer in a VHDL design?

easy

A. To generate random numbers for encryption

B. To increase the clock speed of the system

C. To store data temporarily during processing

D. To detect system failures and trigger a reset if the system stops responding

Solution

1. Step 1: Understand the watchdog timer role

   A watchdog timer monitors system activity to detect failures.

2. Step 2: Identify the correct function

   It triggers a reset if the system stops responding to prevent lockup.

3. Final Answer:

   To detect system failures and trigger a reset if the system stops responding -> Option D

4. Quick Check:

   Watchdog timer = system failure detection [OK]

Hint: Watchdog timer resets system on failure detection [OK]

Common Mistakes:

• Confusing watchdog timer with clock generator
• Thinking it stores data
• Assuming it generates random numbers

2. Which of the following is the correct VHDL signal declaration for a 16-bit counter used in a watchdog timer?

easy

A. signal counter : std_logic_vector(15 downto 0);

B. signal counter : integer range 0 to 15;

C. signal counter : std_logic_vector(0 to 15);

D. signal counter : bit_vector(16 downto 1);

Solution

1. Step 1: Identify correct vector size and direction

   A 16-bit vector uses indices 15 downto 0 for standard logic vectors.

2. Step 2: Check each option

   signal counter : std_logic_vector(15 downto 0); uses std_logic_vector(15 downto 0), which is correct for 16 bits.

3. Final Answer:

   signal counter : std_logic_vector(15 downto 0); -> Option A

4. Quick Check:

   16-bit vector = (15 downto 0) [OK]

Hint: Use downto for descending bit ranges in vectors [OK]

Common Mistakes:

• Using integer range 0 to 15 instead of vector
• Using ascending range (0 to 15) incorrectly
• Using bit_vector instead of std_logic_vector

3. Given this VHDL process snippet for a watchdog timer counter:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What happens to counter when kick is '1'?

medium

A. Counter resets to zero

B. Counter increments by one

C. Counter holds its current value

D. Counter resets to all ones

Solution

1. Step 1: Analyze the condition when kick = '1'

   The code sets counter to (others => '0'), which means all bits zero.

2. Step 2: Understand the effect on counter

   Counter resets to zero instead of incrementing.

3. Final Answer:

   Counter resets to zero -> Option A

4. Quick Check:

   kick '1' resets counter = zero [OK]

Hint: kick '1' means reset counter to zero [OK]

Common Mistakes:

• Assuming counter increments on kick
• Thinking counter holds value on kick
• Confusing reset value with all ones

4. Identify the error in this VHDL watchdog timer process:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using rising_edge(clk) incorrectly

B. Assigning integer 0 to a std_logic_vector signal

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check signal type and assignment

   Counter is usually std_logic_vector; assigning integer 0 directly is invalid.

2. Step 2: Identify correct assignment method

   Must assign (others => '0') or convert integer to vector properly.

3. Final Answer:

   Assigning integer 0 to a std_logic_vector signal -> Option B

4. Quick Check:

   std_logic_vector needs vector assignment, not integer [OK]

Hint: Assign vectors with (others=>'0'), not integer 0 [OK]

Common Mistakes:

• Assigning integer directly to vector
• Ignoring reset conditions
• Misusing clock edge detection

5. You want to design a watchdog timer in VHDL that triggers a timeout signal when the counter reaches 1000 without a kick. Which approach correctly implements this behavior?

hard

A. Increment counter only when kick = '1'; reset counter when timeout = '1'; set timeout when counter > 1000

B. Reset counter on timeout; increment counter only when kick = '1'; set timeout when counter = 1000

C. Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000

D. Set timeout to '1' every clock cycle; reset counter only when kick = '0'

Solution

1. Step 1: Understand watchdog timer logic

   Counter increments every clock cycle unless reset by kick signal.

2. Step 2: Identify correct timeout condition

   Timeout triggers when counter reaches 1000 without reset.

3. Step 3: Evaluate options

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 matches correct logic: increment, reset on kick, timeout at 1000.

4. Final Answer:

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 -> Option C

5. Quick Check:

   Watchdog counts up, resets on kick, timeout at limit [OK]

Hint: Count up, reset on kick, timeout at limit [OK]

Common Mistakes:

• Incrementing only on kick
• Setting timeout every cycle
• Resetting counter incorrectly