Clock domain considerations in VHDL

Introduction

Different parts of a digital circuit can run on different clocks. We need to handle these carefully to avoid mistakes when signals move between them.

When you have multiple clocks in your design, like one fast and one slow clock.

When data moves from one clock area to another, like from a sensor clock to a processor clock.

When you want to avoid errors caused by signals changing at the wrong time.

When designing FPGA or ASIC circuits with multiple clock sources.

When you want to make sure your design works reliably and safely.

Syntax

VHDL

-- Example of synchronizing a signal between clock domains
process(clk_dest) is
  variable sync_1 : std_logic := '0';
  variable sync_2 : std_logic := '0';
begin
  if rising_edge(clk_dest) then
    sync_1 := signal_from_clk_src;
    sync_2 := sync_1;
  end if;
end process;

Use a chain of flip-flops (usually two) to safely transfer signals between clock domains.

Always use rising_edge or falling_edge to detect clock edges in VHDL.

Examples

This example shows how to synchronize an asynchronous signal into the destination clock domain.

VHDL

-- Simple two-flip-flop synchronizer
process(clk_dest) is
  signal sync_1, sync_2 : std_logic := '0';
begin
  if rising_edge(clk_dest) then
    sync_1 <= async_signal;
    sync_2 <= sync_1;
  end if;
end process;

This shows a handshake method to safely transfer data between two clock domains.

VHDL

-- Using handshake signals between clock domains
-- Sender domain
process(clk_src) is
begin
  if rising_edge(clk_src) then
    if ready = '1' then
      data_valid <= '1';
      data_out <= data_in;
    end if;
  end if;
end process;

-- Receiver domain
process(clk_dest) is
begin
  if rising_edge(clk_dest) then
    if data_valid = '1' then
      data_in_dest <= data_out;
      ack <= '1';
    else
      ack <= '0';
    end if;
  end if;
end process;

Sample Program

This VHDL code shows a simple two-stage synchronizer. It safely brings an asynchronous signal into the destination clock domain by passing it through two flip-flops clocked by clk_dest.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity clock_domain_sync is
  port(
    clk_src : in std_logic;
    clk_dest : in std_logic;
    async_signal : in std_logic;
    sync_signal : out std_logic
  );
end entity;

architecture rtl of clock_domain_sync is
  signal sync_1, sync_2 : std_logic := '0';
begin
  process(clk_dest) is
  begin
    if rising_edge(clk_dest) then
      sync_1 <= async_signal;
      sync_2 <= sync_1;
    end if;
  end process;

  sync_signal <= sync_2;
end architecture;

Important Notes

Never connect signals directly between different clock domains without synchronization.

Using two flip-flops reduces the chance of metastability, which can cause unpredictable behavior.

For complex data, use handshake or FIFO methods instead of simple synchronizers.

Summary

Clock domain crossing needs careful handling to avoid errors.

Use two flip-flops to synchronize single-bit signals safely.

For multi-bit data, use handshake or FIFO techniques.

Practice

1. Why is it important to use synchronizers when signals cross different clock domains in VHDL?

easy

A. To reduce power consumption of the circuit

B. To increase the clock frequency of the receiving domain

C. To prevent metastability and ensure reliable data transfer

D. To simplify the VHDL code syntax

Solution

1. Step 1: Understand metastability in clock domain crossing

   When a signal changes asynchronously between two clock domains, the receiving flip-flop can enter an unstable state called metastability.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to reduce the chance of metastability affecting the receiving domain, ensuring reliable data transfer.

3. Final Answer:

   To prevent metastability and ensure reliable data transfer -> Option C

4. Quick Check:

   Synchronizers prevent metastability = C [OK]

Hint: Synchronizers prevent unstable signals crossing clocks [OK]

Common Mistakes:

• Thinking synchronizers increase clock speed
• Assuming synchronizers reduce power
• Believing synchronizers simplify code syntax

2. Which of the following VHDL code snippets correctly implements a 2-stage synchronizer for a single-bit signal async_sig crossing into clk domain?

easy

A. process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

B. process(clk) begin if rising_edge(clk) then sync2 <= async_sig; sync1 <= sync2; end if; end process;

C. process(clk) begin if falling_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process;

D. process(clk) begin if rising_edge(clk) then sync1 <= sync2; sync2 <= async_sig; end if; end process;

Solution

1. Step 1: Identify correct flip-flop sequence

   The first flip-flop captures the asynchronous signal, the second flip-flop captures the first flip-flop's output.

2. Step 2: Check clock edge and assignment order

   Using rising_edge(clk) is standard, and assignments must be in order: sync1 <= async_sig; sync2 <= sync1;

3. Final Answer:

   process(clk) begin if rising_edge(clk) then sync1 <= async_sig; sync2 <= sync1; end if; end process; -> Option A

4. Quick Check:

   Correct order and clock edge = A [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Swapping sync1 and sync2 assignments
• Using falling_edge instead of rising_edge
• Assigning signals in wrong order

3. Given the following VHDL code snippet crossing clock domains, what is the expected behavior of sync2 signal after several clock cycles?

signal async_sig : std_logic;
signal sync1, sync2 : std_logic;

process(clk) begin
  if rising_edge(clk) then
    sync1 <= async_sig;
    sync2 <= sync1;
  end if;
end process;

medium

A. sync2 will immediately match async_sig with no delay

B. sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles

C. sync2 will always be the inverse of async_sig

D. sync2 will cause a runtime error due to signal conflict

Solution

1. Step 1: Understand signal propagation through flip-flops

   sync1 captures async_sig at rising edge, sync2 captures sync1 at next rising edge, causing a two-cycle delay.

2. Step 2: Resulting behavior of sync2

   sync2 becomes a stable, synchronized version of async_sig delayed by two clock cycles, reducing metastability risk.

3. Final Answer:

   sync2 will be a stable, synchronized version of async_sig delayed by two clock cycles -> Option B

4. Quick Check:

   Two flip-flop delay = stable sync2 = A [OK]

Hint: Two flip-flops add two clock cycle delay for stable sync [OK]

Common Mistakes:

• Expecting no delay in sync2
• Thinking sync2 inverts async_sig
• Assuming runtime errors from this code

4. Identify the problem in this VHDL code snippet intended to synchronize a single-bit signal async_sig crossing into clk domain:

process(clk) begin
  if rising_edge(clk) then
    sync2 <= async_sig;
    sync1 <= sync2;
  end if;
end process;

medium

A. The signals sync1 and sync2 are not declared

B. The clock edge should be falling_edge(clk) instead of rising_edge(clk)

C. The process is missing a reset signal

D. The assignments are reversed; sync1 should capture async_sig first

Solution

1. Step 1: Analyze assignment order in process

   sync2 is assigned async_sig first, then sync1 is assigned sync2, which reverses the intended synchronizer chain.

2. Step 2: Correct synchronizer order

   Proper synchronizer assigns sync1 <= async_sig; then sync2 <= sync1; to ensure correct data flow and metastability reduction.

3. Final Answer:

   The assignments are reversed; sync1 should capture async_sig first -> Option D

4. Quick Check:

   Assignment order matters = reversed order = D [OK]

Hint: First flip-flop captures async signal, second captures first [OK]

Common Mistakes:

• Changing clock edge unnecessarily
• Assuming reset is mandatory here
• Ignoring signal declarations

5. You need to transfer an 8-bit data bus async_data from an asynchronous clock domain to a clk domain in VHDL. Which method is the safest and most reliable to avoid data corruption?

hard

A. Use a handshake protocol with ready/acknowledge signals between domains

B. Use a single 2-stage synchronizer on each bit of the data bus

C. Directly assign async_data to a register in the clk domain

D. Use a combinational logic block to pass data asynchronously

Solution

1. Step 1: Understand complexity of multi-bit data crossing clock domains

   Multi-bit data can change asynchronously, causing partial updates and data corruption if not handled carefully.

2. Step 2: Choose proper synchronization method

   Handshake protocols with ready/acknowledge signals ensure data is stable and fully transferred before use, avoiding corruption.

3. Final Answer:

   Use a handshake protocol with ready/acknowledge signals between domains -> Option A

4. Quick Check:

   Handshake ensures safe multi-bit transfer = B [OK]

Hint: Use handshake or FIFO for multi-bit async data transfer [OK]

Common Mistakes:

• Using single-bit synchronizers on multi-bit buses
• Direct asynchronous assignments causing glitches
• Relying on combinational logic for async crossing