I2C controller basics in VHDL

Introduction

I2C controllers help devices talk to each other using just two wires. This makes communication simple and saves space.

Connecting sensors to a microcontroller with few wires.

Making small devices like displays communicate with a main chip.

Sharing data between chips inside a gadget without many wires.

Syntax

VHDL

entity I2C_Controller is
  Port (
    clk       : in  std_logic;
    reset     : in  std_logic;
    scl       : inout std_logic;
    sda       : inout std_logic;
    start     : in  std_logic;
    stop      : in  std_logic;
    data_in   : in  std_logic_vector(7 downto 0);
    data_out  : out std_logic_vector(7 downto 0);
    ack       : out std_logic
  );
end I2C_Controller;

The entity defines the I2C controller's inputs and outputs.

scl and sda are bidirectional lines used for clock and data.

Examples

Control the clock and data lines by setting them low or releasing them high.

VHDL

scl <= '0'; -- Pull clock line low
sda <= '1'; -- Release data line

Use a clocked process to detect the start condition and control communication.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if start = '1' then
      -- Begin I2C communication
    end if;
  end if;
end process;

Sample Program

This simple I2C controller example shows how to create start and stop conditions by controlling the SDA line while SCL stays high.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity I2C_Controller is
  Port (
    clk       : in  std_logic;
    reset     : in  std_logic;
    scl       : inout std_logic;
    sda       : inout std_logic;
    start     : in  std_logic;
    stop      : in  std_logic;
    data_in   : in  std_logic_vector(7 downto 0);
    data_out  : out std_logic_vector(7 downto 0);
    ack       : out std_logic
  );
end I2C_Controller;

architecture Behavioral of I2C_Controller is
  signal sda_internal : std_logic := '1';
  signal scl_internal : std_logic := '1';
begin
  -- Simple example: drive sda low on start
  process(clk, reset)
  begin
    if reset = '1' then
      sda_internal <= '1';
      scl_internal <= '1';
      ack <= '0';
      data_out <= (others => '0');
    elsif rising_edge(clk) then
      if start = '1' then
        sda_internal <= '0'; -- Start condition: SDA goes low while SCL is high
      elsif stop = '1' then
        sda_internal <= '1'; -- Stop condition: SDA goes high while SCL is high
      end if;
    end if;
  end process;

  sda <= sda_internal;
  scl <= scl_internal;
end Behavioral;

Important Notes

I2C uses two lines: SCL (clock) and SDA (data), both open-drain, meaning devices can only pull lines low or release them.

Start condition: SDA changes from high to low while SCL is high.

Stop condition: SDA changes from low to high while SCL is high.

Summary

I2C controllers manage communication using two wires: clock and data.

Start and stop conditions control when communication begins and ends.

VHDL code controls these lines to implement I2C behavior.

Practice

1. What are the two main signals controlled by an I2C controller in VHDL?

easy

A. CLK and RESET

B. TX and RX

C. MOSI and MISO

D. SCL (clock) and SDA (data)

Solution

1. Step 1: Understand I2C communication basics

   I2C uses two wires: one for clock (SCL) and one for data (SDA).

2. Step 2: Identify signals controlled by the controller

   The I2C controller manages these two lines to send and receive data.

3. Final Answer:

   SCL (clock) and SDA (data) -> Option D

4. Quick Check:

   I2C signals = SCL and SDA [OK]

Hint: Remember: I2C always uses clock and data lines [OK]

Common Mistakes:

• Confusing I2C signals with SPI signals
• Thinking TX/RX are used in I2C
• Mixing up clock and reset signals

2. Which VHDL statement correctly declares the SDA line as an output signal in an I2C controller?

easy

A. signal SDA : out std_logic;

B. signal SDA : in std_logic;

C. signal SDA : buffer std_logic;

D. signal SDA : inout std_logic;

Solution

1. Step 1: Recall VHDL signal directions

   Output signals are declared with the keyword 'out'.

2. Step 2: Match SDA line direction

   SDA is controlled by the I2C controller to send data, so it must be 'out'.

3. Final Answer:

   signal SDA : out std_logic; -> Option A

4. Quick Check:

   Output signal = 'out' [OK]

Hint: Output signals use 'out' keyword in VHDL [OK]

Common Mistakes:

• Using 'in' instead of 'out' for output signals
• Confusing 'buffer' and 'out' keywords
• Using 'inout' when only output is needed

3. Given this VHDL snippet for generating a start condition in I2C, what is the value of SDA after execution?

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '1';
    SCL <= '1';
    SDA <= '0'; -- start condition
  end if;
end process;

medium

A. '1'

B. '0'

C. Undefined (multiple assignments in one clock)

D. Remains previous value

Solution

1. Step 1: Analyze signal assignments in process

   Within the same clock edge, SDA is first set to '1', then immediately to '0'.

2. Step 2: Understand signal assignment behavior in VHDL

   Last assignment in the process overrides previous ones, so SDA becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Last assignment wins = '0' [OK]

Hint: Last signal assignment in process sets final value [OK]

Common Mistakes:

• Assuming first assignment sticks
• Thinking multiple assignments cause error
• Ignoring VHDL signal update rules

4. Identify the error in this VHDL code snippet for generating a stop condition in I2C:

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '0';
    SCL <= '1';
    SDA <= '1'; -- stop condition
  end if;
end process;

medium

A. SDA should be set to '1' before SCL is '1'

B. No error, code is correct

C. Multiple assignments to SDA in one clock cause conflict

D. Stop condition requires SDA to go low, not high

Solution

1. Step 1: Review SDA assignments in the process

   SDA is assigned '0' then '1' in the same clock cycle.

2. Step 2: Understand VHDL signal assignment rules

   Multiple assignments to the same signal in one clock can cause unexpected behavior or synthesis issues.

3. Final Answer:

   Multiple assignments to SDA in one clock cause conflict -> Option C

4. Quick Check:

   Multiple assignments = conflict [OK]

Hint: Avoid multiple assignments to same signal in one clock [OK]

Common Mistakes:

• Ignoring multiple assignments problem
• Confusing start and stop condition logic
• Assuming code runs without synthesis warnings

5. You want to design an I2C controller in VHDL that sends a start condition, then transmits 8 bits of data, and finally sends a stop condition. Which sequence of signal changes correctly represents this process?

hard

A. SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop)

B. SDA goes low to high while SCL is low (start), then data bits sent on SDA with SCL low, then SDA goes high to low while SCL is low (stop)

C. SCL stays low throughout, SDA toggles for start, data, and stop

D. SDA and SCL both toggle randomly during start, data, and stop

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls from high to low while SCL is high. Stop condition: SDA rises from low to high while SCL is high.

2. Step 2: Understand data transmission timing

   Data bits are sent on SDA line while toggling SCL clock line to synchronize bits.

3. Step 3: Match sequence to options

   SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop) correctly describes the start, data, and stop signal changes.

4. Final Answer:

   Start: SDA high to low while SCL high, data sent with SCL toggling, stop: SDA low to high while SCL high -> Option A

5. Quick Check:

   Start/stop conditions require SDA change while SCL high [OK]

Hint: Start/stop change SDA only when SCL is high [OK]

Common Mistakes:

• Changing SDA when SCL is low for start/stop
• Not toggling SCL during data bits
• Confusing start and stop signal directions