Generic parameters for configurable modules in VHDL

Introduction

Generic parameters let you make a module flexible by setting values before using it. This way, you can reuse the same module with different settings.

When you want to create a module that can work with different data sizes.

When you need to change timing or delay values without rewriting the module.

When you want to reuse the same design but with different configurations.

When you want to make your code easier to maintain by avoiding duplicates.

Syntax

VHDL

entity EntityName is
  generic (
    PARAM_NAME : type := default_value
  );
  port (
    -- ports here
  );
end EntityName;

Generic parameters are like input settings for your module.

You set them when you create an instance of the module.

Examples

This example creates a counter with a configurable bit width.

VHDL

entity Counter is
  generic (
    WIDTH : integer := 8
  );
  port (
    clk : in std_logic;
    count : out std_logic_vector(WIDTH-1 downto 0)
  );
end Counter;

The architecture uses the generic WIDTH to define the size of the counter.

VHDL

architecture Behavioral of Counter is
  signal internal_count : std_logic_vector(WIDTH-1 downto 0) := (others => '0');
begin
  process(clk)
  begin
    if rising_edge(clk) then
      internal_count <= internal_count + 1;
    end if;
  end process;
  count <= internal_count;
end Behavioral;

This shows how to declare the component with the generic parameter.

VHDL

component Counter
  generic (
    WIDTH : integer := 8
  );
  port (
    clk : in std_logic;
    count : out std_logic_vector(WIDTH-1 downto 0)
  );
end component;

This is how to create an instance of the Counter with WIDTH set to 16.

VHDL

U1: Counter
  generic map (WIDTH => 16)
  port map (
    clk => clk_signal,
    count => count_signal
  );

Sample Program

This program defines a counter module with a generic WIDTH. The testbench runs the counter and reports the count value on each clock rising edge until it reaches 15.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Counter is
  generic (
    WIDTH : integer := 4
  );
  port (
    clk : in std_logic;
    count : out std_logic_vector(WIDTH-1 downto 0)
  );
end Counter;

architecture Behavioral of Counter is
  signal internal_count : unsigned(WIDTH-1 downto 0) := (others => '0');
begin
  process(clk)
  begin
    if rising_edge(clk) then
      internal_count <= internal_count + 1;
    end if;
  end process;
  count <= std_logic_vector(internal_count);
end Behavioral;

-- Testbench
entity tb_Counter is
end tb_Counter;

architecture test of tb_Counter is
  signal clk : std_logic := '0';
  signal count : std_logic_vector(3 downto 0);

  component Counter
    generic (
      WIDTH : integer := 4
    );
    port (
      clk : in std_logic;
      count : out std_logic_vector(WIDTH-1 downto 0)
    );
  end component;

begin
  UUT: Counter
    generic map (WIDTH => 4)
    port map (
      clk => clk,
      count => count
    );

  clk_process : process
  begin
    while true loop
      clk <= '0';
      wait for 10 ns;
      clk <= '1';
      wait for 10 ns;
    end loop;
  end process;

  monitor_process : process(clk)
  begin
    if rising_edge(clk) then
      report "Count = " & integer'image(to_integer(unsigned(count)));
      if to_integer(unsigned(count)) = 15 then
        wait;
      end if;
    end if;
  end process;
end test;

Important Notes

You can have multiple generic parameters in one module.

Generic parameters must have a default value or be set when instantiating.

Generics help make your design reusable and easier to change.

Summary

Generic parameters let you customize modules without changing their code.

They are set when you create an instance of the module.

This makes your VHDL code flexible and reusable.

Practice

1. What is the main purpose of generic parameters in a VHDL module?

easy

A. To declare variables local to a process

B. To define signals inside the architecture

C. To specify the clock frequency of the design

D. To customize module behavior without changing its internal code

Solution

1. Step 1: Understand the role of generics in VHDL

   Generics allow you to set parameters that can change module behavior without rewriting the module code.

2. Step 2: Compare with other options

   Signals and variables are different constructs; generics are not for clock frequency specifically.

3. Final Answer:

   To customize module behavior without changing its internal code -> Option D

4. Quick Check:

   Generics = customizable parameters [OK]

Hint: Generics customize modules without code changes [OK]

Common Mistakes:

• Confusing generics with signals or variables
• Thinking generics set clock frequency only
• Assuming generics are declared inside architecture

2. Which of the following is the correct syntax to declare a generic parameter named WIDTH of type integer with default value 8 in a VHDL entity?

easy

A. constant WIDTH : integer := 8;

B. generic WIDTH : integer = 8;

C. generic (WIDTH : integer := 8);

D. parameter WIDTH : integer := 8;

Solution

1. Step 1: Recall VHDL generic declaration syntax

   Generics are declared inside parentheses after the keyword generic with colon and default value using :=.

2. Step 2: Check each option

   generic (WIDTH : integer := 8); matches correct syntax: generic (WIDTH : integer := 8);. Others use incorrect keywords or syntax.

3. Final Answer:

   generic (WIDTH : integer := 8); -> Option C

4. Quick Check:

   Generic syntax uses parentheses and := [OK]

Hint: Generics use parentheses and := for defaults [OK]

Common Mistakes:

• Using '=' instead of ':=' for default values
• Confusing generics with constants or parameters
• Omitting parentheses around generic list

3. Given the following VHDL entity and architecture:

entity MyModule is
  generic (WIDTH : integer := 4);
  port (
    input : in std_logic_vector(WIDTH-1 downto 0);
    output : out std_logic_vector(WIDTH-1 downto 0)
  );
end MyModule;

architecture Behavioral of MyModule is
begin
  output <= input;
end Behavioral;

What will be the width of output if this module is instantiated with generic map (WIDTH => 8)?

medium

A. 8 bits

B. 4 bits

C. WIDTH bits (unknown)

D. 1 bit

Solution

1. Step 1: Understand generic override on instantiation

   The generic WIDTH default is 4, but overridden to 8 during instantiation.

2. Step 2: Calculate output width

   Output is std_logic_vector(WIDTH-1 downto 0), so with WIDTH=8, output is 8 bits wide.

3. Final Answer:

   8 bits -> Option A

4. Quick Check:

   Generic override sets WIDTH=8 [OK]

Hint: Generic override changes WIDTH to 8 bits [OK]

Common Mistakes:

• Ignoring generic override and using default 4
• Confusing WIDTH with signal length
• Assuming output is always 1 bit

4. Identify the error in this VHDL entity declaration:

entity ConfigurableCounter is
  generic WIDTH : integer := 8;
  port (
    clk : in std_logic;
    count : out std_logic_vector(WIDTH-1 downto 0)
  );
end ConfigurableCounter;

medium

A. Missing parentheses around generic declaration

B. WIDTH should be declared as a signal, not generic

C. Port declaration syntax is incorrect

D. No error, declaration is correct

Solution

1. Step 1: Check generic declaration syntax

   Generics must be declared inside parentheses after the keyword generic.

2. Step 2: Analyze given code

   The code declares generic WIDTH : integer := 8; without parentheses, which is invalid syntax.

3. Final Answer:

   Missing parentheses around generic declaration -> Option A

4. Quick Check:

   Generics need parentheses [OK]

Hint: Always use parentheses for generics [OK]

Common Mistakes:

• Omitting parentheses in generic declaration
• Confusing generics with signals
• Assuming port syntax is wrong when it's correct

5. You want to create a VHDL module for a FIFO buffer where the depth and data width can be set using generics. Which of the following is the best way to declare these generics in the entity?

hard

A. generic DEPTH : integer := 16; WIDTH : integer := 8;

B. generic (DEPTH : integer := 16; WIDTH : integer := 8);

C. constant DEPTH : integer := 16; constant WIDTH : integer := 8;

D. signal DEPTH : integer := 16; signal WIDTH : integer := 8;

Solution

1. Step 1: Recall correct generic declaration for multiple parameters

   Multiple generics must be declared inside parentheses separated by semicolons.

2. Step 2: Evaluate each option

   generic (DEPTH : integer := 16; WIDTH : integer := 8); correctly declares both generics inside parentheses with default values. Options B, C, and D use incorrect keywords or syntax.

3. Final Answer:

   generic (DEPTH : integer := 16; WIDTH : integer := 8); -> Option B

4. Quick Check:

   Multiple generics use parentheses and semicolons [OK]

Hint: Use parentheses and semicolons for multiple generics [OK]

Common Mistakes:

• Declaring generics without parentheses
• Using constant or signal instead of generic
• Separating generics with commas instead of semicolons