Watchdog timer design in VHDL - Mini Project: Build & Apply

Watchdog Timer Design in VHDL

📖 Scenario: In embedded systems, a watchdog timer helps to reset the system if it stops responding. This project will guide you to design a simple watchdog timer in VHDL. The timer counts clock cycles and triggers a reset if the system does not send a reset signal in time.

🎯 Goal: You will build a VHDL module for a watchdog timer that counts clock cycles, resets the count on a reset signal, and asserts a timeout signal if the count reaches a set limit.

📋 What You'll Learn

Create a signal to count clock cycles

Define a constant for the timeout limit

Implement counting logic that resets on a reset signal

Output a timeout signal when the count reaches the limit

💡 Why This Matters

🌍 Real World

Watchdog timers are used in embedded systems to detect and recover from software failures by resetting the system if it becomes unresponsive.

💼 Career

Understanding how to design hardware timers and counters in VHDL is essential for FPGA and ASIC design engineers working on reliable embedded systems.

1

Create the basic entity and architecture with clock and reset inputs

Write the VHDL code to declare an entity called watchdog_timer with inputs clk and reset_in, and outputs timeout. Then start the architecture declaration with a signal counter of type unsigned(7 downto 0) initialized to zero.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity watchdog_timer is
    port (
        clk : in std_logic;
        reset_in : in std_logic;
        timeout : out std_logic
    );
end watchdog_timer;

architecture Behavioral of watchdog_timer is
    signal counter : unsigned(7 downto 0) := (others => '0');
begin
    -- Your code here
end Behavioral;

Hint

Start by declaring the entity with the exact ports and then declare the architecture with the counter signal.

2

Add a constant for the timeout limit

Inside the architecture Behavioral, declare a constant called TIMEOUT_LIMIT of type unsigned(7 downto 0) and set it to "11111111" (255 in binary).

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity watchdog_timer is
    port (
        clk : in std_logic;
        reset_in : in std_logic;
        timeout : out std_logic
    );
end watchdog_timer;

architecture Behavioral of watchdog_timer is
    signal counter : unsigned(7 downto 0) := (others => '0');
    -- Declare TIMEOUT_LIMIT constant here
    -- Your code here
begin
    -- Counting logic will be added later
end Behavioral;

Hint

Use the constant keyword and assign the binary string "11111111" to represent 255.

3

Implement the counting logic with reset and timeout detection

Inside the architecture Behavioral, add a process sensitive to clk. On the rising edge of clk, if reset_in is '1', reset counter to zero. Otherwise, if counter is less than TIMEOUT_LIMIT, increment counter by 1.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity watchdog_timer is
    port (
        clk : in std_logic;
        reset_in : in std_logic;
        timeout : out std_logic
    );
end watchdog_timer;

architecture Behavioral of watchdog_timer is
    signal counter : unsigned(7 downto 0) := (others => '0');
    constant TIMEOUT_LIMIT : unsigned(7 downto 0) := "11111111";
begin
    process(clk)
    begin
        if rising_edge(clk) then
            -- Your code here
        end if;
    end process;
end Behavioral;

Hint

Use a process triggered by clk. Inside, check for rising edge, then reset or increment the counter.

4

Output the timeout signal when the counter reaches the limit

Add a concurrent assignment to set timeout to '1' when counter equals TIMEOUT_LIMIT, otherwise '0'. Then print the value of timeout in a testbench or simulation to verify.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity watchdog_timer is
    port (
        clk : in std_logic;
        reset_in : in std_logic;
        timeout : out std_logic
    );
end watchdog_timer;

architecture Behavioral of watchdog_timer is
    signal counter : unsigned(7 downto 0) := (others => '0');
    constant TIMEOUT_LIMIT : unsigned(7 downto 0) := "11111111";
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if reset_in = '1' then
                counter  '0');
            elsif counter < TIMEOUT_LIMIT then
                counter <= counter + 1;
            end if;
        end if;
    end process;

    -- Assign timeout signal here
    -- Your code here
end Behavioral;

Hint

Use a concurrent signal assignment with a conditional expression to set timeout.

Practice

1. What is the main purpose of a watchdog timer in a VHDL design?

easy

A. To generate random numbers for encryption

B. To increase the clock speed of the system

C. To store data temporarily during processing

D. To detect system failures and trigger a reset if the system stops responding

Solution

1. Step 1: Understand the watchdog timer role

   A watchdog timer monitors system activity to detect failures.

2. Step 2: Identify the correct function

   It triggers a reset if the system stops responding to prevent lockup.

3. Final Answer:

   To detect system failures and trigger a reset if the system stops responding -> Option D

4. Quick Check:

   Watchdog timer = system failure detection [OK]

Hint: Watchdog timer resets system on failure detection [OK]

Common Mistakes:

• Confusing watchdog timer with clock generator
• Thinking it stores data
• Assuming it generates random numbers

2. Which of the following is the correct VHDL signal declaration for a 16-bit counter used in a watchdog timer?

easy

A. signal counter : std_logic_vector(15 downto 0);

B. signal counter : integer range 0 to 15;

C. signal counter : std_logic_vector(0 to 15);

D. signal counter : bit_vector(16 downto 1);

Solution

1. Step 1: Identify correct vector size and direction

   A 16-bit vector uses indices 15 downto 0 for standard logic vectors.

2. Step 2: Check each option

   signal counter : std_logic_vector(15 downto 0); uses std_logic_vector(15 downto 0), which is correct for 16 bits.

3. Final Answer:

   signal counter : std_logic_vector(15 downto 0); -> Option A

4. Quick Check:

   16-bit vector = (15 downto 0) [OK]

Hint: Use downto for descending bit ranges in vectors [OK]

Common Mistakes:

• Using integer range 0 to 15 instead of vector
• Using ascending range (0 to 15) incorrectly
• Using bit_vector instead of std_logic_vector

3. Given this VHDL process snippet for a watchdog timer counter:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What happens to counter when kick is '1'?

medium

A. Counter resets to zero

B. Counter increments by one

C. Counter holds its current value

D. Counter resets to all ones

Solution

1. Step 1: Analyze the condition when kick = '1'

   The code sets counter to (others => '0'), which means all bits zero.

2. Step 2: Understand the effect on counter

   Counter resets to zero instead of incrementing.

3. Final Answer:

   Counter resets to zero -> Option A

4. Quick Check:

   kick '1' resets counter = zero [OK]

Hint: kick '1' means reset counter to zero [OK]

Common Mistakes:

• Assuming counter increments on kick
• Thinking counter holds value on kick
• Confusing reset value with all ones

4. Identify the error in this VHDL watchdog timer process:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using rising_edge(clk) incorrectly

B. Assigning integer 0 to a std_logic_vector signal

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check signal type and assignment

   Counter is usually std_logic_vector; assigning integer 0 directly is invalid.

2. Step 2: Identify correct assignment method

   Must assign (others => '0') or convert integer to vector properly.

3. Final Answer:

   Assigning integer 0 to a std_logic_vector signal -> Option B

4. Quick Check:

   std_logic_vector needs vector assignment, not integer [OK]

Hint: Assign vectors with (others=>'0'), not integer 0 [OK]

Common Mistakes:

• Assigning integer directly to vector
• Ignoring reset conditions
• Misusing clock edge detection

5. You want to design a watchdog timer in VHDL that triggers a timeout signal when the counter reaches 1000 without a kick. Which approach correctly implements this behavior?

hard

A. Increment counter only when kick = '1'; reset counter when timeout = '1'; set timeout when counter > 1000

B. Reset counter on timeout; increment counter only when kick = '1'; set timeout when counter = 1000

C. Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000

D. Set timeout to '1' every clock cycle; reset counter only when kick = '0'

Solution

1. Step 1: Understand watchdog timer logic

   Counter increments every clock cycle unless reset by kick signal.

2. Step 2: Identify correct timeout condition

   Timeout triggers when counter reaches 1000 without reset.

3. Step 3: Evaluate options

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 matches correct logic: increment, reset on kick, timeout at 1000.

4. Final Answer:

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 -> Option C

5. Quick Check:

   Watchdog counts up, resets on kick, timeout at limit [OK]

Hint: Count up, reset on kick, timeout at limit [OK]

Common Mistakes:

• Incrementing only on kick
• Setting timeout every cycle
• Resetting counter incorrectly