Resource inference rules in VHDL

Introduction

Resource inference rules help the VHDL compiler decide which hardware parts to create from your code automatically.

When you write VHDL code and want the compiler to create hardware like flip-flops or RAM for you.

When you want to save time by not manually specifying hardware components.

When you want your design to be portable across different FPGA or ASIC devices.

When you want to optimize hardware usage by letting the compiler choose the best implementation.

Syntax

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      reg <= data_in;
    end if;
  end if;
end process;

This example shows a simple register inferred by the compiler.

The compiler uses your code style to decide which hardware to create.

Examples

This infers a simple flip-flop (register) that stores data on clock edge.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    reg <= data_in;
  end if;
end process;

This infers a small RAM block with write enable and address.

VHDL

type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);
signal ram : ram_type;

process(clk)
begin
  if rising_edge(clk) then
    if we = '1' then
      ram(addr) <= data_in;
    end if;
    data_out <= ram(addr);
  end if;
end process;

This infers a counter with synchronous reset.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      count <= (others => '0');
    else
      count <= count + 1;
    end if;
  end if;
end process;

Sample Program

This program shows a simple register that stores 4-bit data when enable is high on clock rising edge.

The VHDL compiler will infer a flip-flop hardware for this register automatically.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simple_register is
  port(
    clk : in std_logic;
    enable : in std_logic;
    data_in : in std_logic_vector(3 downto 0);
    data_out : out std_logic_vector(3 downto 0)
  );
end simple_register;

architecture behavioral of simple_register is
  signal reg : std_logic_vector(3 downto 0);
begin
  process(clk)
  begin
    if rising_edge(clk) then
      if enable = '1' then
        reg <= data_in;
      end if;
    end if;
  end process;
  data_out <= reg;
end behavioral;

Important Notes

Resource inference depends on how you write your VHDL code.

Different synthesis tools may infer hardware differently from the same code.

Always check synthesis reports to understand what hardware was created.

Summary

Resource inference rules let the compiler create hardware from your VHDL code automatically.

Writing code in certain ways helps the compiler infer registers, RAM, counters, and more.

This saves time and makes your design easier to move between devices.

Practice

1. Which VHDL construct typically causes the compiler to infer a register (flip-flop)?

easy

A. A clocked process with a rising_edge(clock) condition

B. A simple concurrent signal assignment

C. A combinational process without clock sensitivity

D. A constant declaration

Solution

1. Step 1: Understand what infers registers

   Registers (flip-flops) are inferred when signals are assigned inside a process triggered by a clock edge, such as rising_edge(clock).

2. Step 2: Identify the correct construct

   A clocked process with rising_edge(clock) matches this condition, so it infers registers.

3. Final Answer:

   A clocked process with a rising_edge(clock) condition -> Option A

4. Quick Check:

   Clocked process = register inference [OK]

Hint: Registers come from clocked processes with edge checks [OK]

Common Mistakes:

• Confusing combinational assignments with registers
• Thinking constants infer registers
• Ignoring the clock edge condition

2. Which of the following VHDL code snippets correctly infers combinational logic?

easy

A. q <= a and b;

B. signal r : std_logic_vector(3 downto 0);

C. constant c : integer := 5;

D. process(clk) begin if rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify combinational logic inference

   Combinational logic is inferred from concurrent signal assignments or processes without clock edges.

2. Step 2: Check each option

   q <= a and b; is a concurrent assignment using logical AND, which infers combinational logic.

3. Final Answer:

   q <= a and b; -> Option A

4. Quick Check:

   Concurrent assignment = combinational logic [OK]

Hint: Combinational logic comes from simple concurrent assignments [OK]

Common Mistakes:

• Choosing clocked processes for combinational logic
• Confusing constants or signals with logic inference
• Ignoring the absence of clock edges

3. Given the following VHDL code, what hardware resource is inferred?

process(clk, a, b)
begin
  if rising_edge(clk) then
    q <= a or b;
  end if;
end process;

medium

A. Combinational logic only

B. Register (flip-flop) with combinational logic inside

C. Constant value

D. Latch

Solution

1. Step 1: Analyze the process sensitivity and clock usage

   The process is sensitive to clk, a, and b, but the assignment happens only on rising_edge(clk), indicating a clocked process.

2. Step 2: Determine inferred hardware

   Because the assignment is inside a clock edge condition, a register (flip-flop) is inferred. The expression 'a or b' is combinational logic feeding the register input.

3. Final Answer:

   Register (flip-flop) with combinational logic inside -> Option B

4. Quick Check:

   Clock edge + logic = register with combinational input [OK]

Hint: Clock edge inside process means register inferred [OK]

Common Mistakes:

• Ignoring the clock edge and thinking it's pure combinational
• Confusing latch with register
• Assuming constants are inferred

4. Identify the error in this VHDL code that prevents correct resource inference:

process(clk)
begin
  if clk = '1' then
    q <= d;
  end if;
end process;

medium

A. Signal q is not declared

B. Process sensitivity list is empty

C. Missing rising_edge(clk) condition for clocked process

D. Constant d is used instead of signal

Solution

1. Step 1: Check clock condition usage

   The process uses 'if clk = '1'' instead of 'if rising_edge(clk)', which is the standard way to infer registers.

2. Step 2: Understand impact on resource inference

   Without rising_edge(clk), the compiler may infer a latch or incorrect hardware instead of a register.

3. Final Answer:

   Missing rising_edge(clk) condition for clocked process -> Option C

4. Quick Check:

   Use rising_edge(clk) for registers [OK]

Hint: Always use rising_edge(clk) for registers [OK]

Common Mistakes:

• Using level-sensitive clock check instead of edge
• Ignoring sensitivity list correctness
• Assuming signal declarations cause inference errors

5. You want to infer a 4-bit register with asynchronous reset in VHDL. Which code snippet correctly follows resource inference rules?

hard

A. process(reset) begin if reset = '1' then q <= (others => '0'); end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= (others => '0'); else q <= d; end if; end if; end process;

C. q <= d when reset = '0' else (others => '0');

D. process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process;

Solution

1. Step 1: Identify asynchronous reset structure

   An asynchronous reset requires the reset signal in the sensitivity list and a separate if condition before the clock edge check.

2. Step 2: Check each option for correct inference

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; has reset and clk in sensitivity list, checks reset first, then rising_edge(clk), correctly inferring a register with async reset.

3. Final Answer:

   process(clk, reset) begin if reset = '1' then q <= (others => '0'); elsif rising_edge(clk) then q <= d; end if; end process; -> Option D

4. Quick Check:

   Async reset in sensitivity + if reset first = correct [OK]

Hint: Async reset must be checked before clock edge in process [OK]

Common Mistakes:

• Placing reset check inside clock edge condition (sync reset)
• Missing reset in sensitivity list for async reset
• Using conditional assignments outside process for registers