Watchdog timer design in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the main purpose of a watchdog timer in digital systems?

A watchdog timer helps detect and recover from system failures by resetting the system if it stops responding within a set time.

beginner

In VHDL, what basic components are needed to build a watchdog timer?

You need a counter to track time, a reset signal to restart the counter, and a timeout signal to trigger a system reset if the counter reaches a limit.

beginner

Why is it important to 'kick' or 'refresh' the watchdog timer regularly?

Refreshing the watchdog timer prevents it from timing out and resetting the system, indicating the system is still working correctly.

beginner

What happens when the watchdog timer reaches its timeout value without being reset?

The watchdog timer triggers a reset signal to restart the system, helping recover from a possible system hang or failure.

intermediate

How can you test a watchdog timer design in VHDL simulation?

You can simulate the system not refreshing the watchdog and check if the reset signal activates after the timeout period.

What is the role of the counter in a watchdog timer design?

A To count clock cycles until timeout

B To store system data

C To generate random numbers

D To control input signals

The counter tracks time by counting clock cycles until it reaches the timeout value.

What signal should be sent to the watchdog timer to prevent it from resetting the system?

A Reset signal

B Enable signal

C Refresh or kick signal

D Timeout signal

The refresh or kick signal resets the watchdog timer counter to prevent timeout.

If the watchdog timer is not refreshed, what is the expected outcome?

A System continues normally

B Counter resets automatically

C System clock stops

D System reset is triggered

Without refresh, the watchdog timer times out and triggers a system reset.

Which VHDL construct is commonly used to implement the timing behavior of a watchdog timer?

A Process with clock sensitivity

B Function call

C Package declaration

D Component instantiation

A process sensitive to the clock signal is used to increment the counter and check timeout.

What is a good practice when designing a watchdog timer for safety-critical systems?

A Disable the watchdog during operation

B Ensure the timeout is long enough to avoid false resets

C Use a very short timeout

D Remove the refresh signal

Timeout should be long enough to avoid resetting during normal operation but short enough to catch failures.

Explain how a watchdog timer works and why it is important in digital systems.

Think about how the system knows if it is stuck and what the watchdog does to fix it.

Describe the key VHDL components and signals you would use to design a simple watchdog timer.

Consider what parts keep track of time and what triggers a reset.

Practice

1. What is the main purpose of a watchdog timer in a VHDL design?

easy

A. To generate random numbers for encryption

B. To increase the clock speed of the system

C. To store data temporarily during processing

D. To detect system failures and trigger a reset if the system stops responding

Solution

1. Step 1: Understand the watchdog timer role

   A watchdog timer monitors system activity to detect failures.

2. Step 2: Identify the correct function

   It triggers a reset if the system stops responding to prevent lockup.

3. Final Answer:

   To detect system failures and trigger a reset if the system stops responding -> Option D

4. Quick Check:

   Watchdog timer = system failure detection [OK]

Hint: Watchdog timer resets system on failure detection [OK]

Common Mistakes:

• Confusing watchdog timer with clock generator
• Thinking it stores data
• Assuming it generates random numbers

2. Which of the following is the correct VHDL signal declaration for a 16-bit counter used in a watchdog timer?

easy

A. signal counter : std_logic_vector(15 downto 0);

B. signal counter : integer range 0 to 15;

C. signal counter : std_logic_vector(0 to 15);

D. signal counter : bit_vector(16 downto 1);

Solution

1. Step 1: Identify correct vector size and direction

   A 16-bit vector uses indices 15 downto 0 for standard logic vectors.

2. Step 2: Check each option

   signal counter : std_logic_vector(15 downto 0); uses std_logic_vector(15 downto 0), which is correct for 16 bits.

3. Final Answer:

   signal counter : std_logic_vector(15 downto 0); -> Option A

4. Quick Check:

   16-bit vector = (15 downto 0) [OK]

Hint: Use downto for descending bit ranges in vectors [OK]

Common Mistakes:

• Using integer range 0 to 15 instead of vector
• Using ascending range (0 to 15) incorrectly
• Using bit_vector instead of std_logic_vector

3. Given this VHDL process snippet for a watchdog timer counter:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What happens to counter when kick is '1'?

medium

A. Counter resets to zero

B. Counter increments by one

C. Counter holds its current value

D. Counter resets to all ones

Solution

1. Step 1: Analyze the condition when kick = '1'

   The code sets counter to (others => '0'), which means all bits zero.

2. Step 2: Understand the effect on counter

   Counter resets to zero instead of incrementing.

3. Final Answer:

   Counter resets to zero -> Option A

4. Quick Check:

   kick '1' resets counter = zero [OK]

Hint: kick '1' means reset counter to zero [OK]

Common Mistakes:

• Assuming counter increments on kick
• Thinking counter holds value on kick
• Confusing reset value with all ones

4. Identify the error in this VHDL watchdog timer process:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using rising_edge(clk) incorrectly

B. Assigning integer 0 to a std_logic_vector signal

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check signal type and assignment

   Counter is usually std_logic_vector; assigning integer 0 directly is invalid.

2. Step 2: Identify correct assignment method

   Must assign (others => '0') or convert integer to vector properly.

3. Final Answer:

   Assigning integer 0 to a std_logic_vector signal -> Option B

4. Quick Check:

   std_logic_vector needs vector assignment, not integer [OK]

Hint: Assign vectors with (others=>'0'), not integer 0 [OK]

Common Mistakes:

• Assigning integer directly to vector
• Ignoring reset conditions
• Misusing clock edge detection

5. You want to design a watchdog timer in VHDL that triggers a timeout signal when the counter reaches 1000 without a kick. Which approach correctly implements this behavior?

hard

A. Increment counter only when kick = '1'; reset counter when timeout = '1'; set timeout when counter > 1000

B. Reset counter on timeout; increment counter only when kick = '1'; set timeout when counter = 1000

C. Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000

D. Set timeout to '1' every clock cycle; reset counter only when kick = '0'

Solution

1. Step 1: Understand watchdog timer logic

   Counter increments every clock cycle unless reset by kick signal.

2. Step 2: Identify correct timeout condition

   Timeout triggers when counter reaches 1000 without reset.

3. Step 3: Evaluate options

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 matches correct logic: increment, reset on kick, timeout at 1000.

4. Final Answer:

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 -> Option C

5. Quick Check:

   Watchdog counts up, resets on kick, timeout at limit [OK]

Hint: Count up, reset on kick, timeout at limit [OK]

Common Mistakes:

• Incrementing only on kick
• Setting timeout every cycle
• Resetting counter incorrectly