Synthesizable vs non-synthesizable constructs in VHDL

Introduction

We use synthesizable constructs to create hardware circuits from VHDL code. Non-synthesizable constructs help us test and simulate designs but cannot become hardware.

When writing code that will turn into real hardware, like a circuit on an FPGA.

When creating testbenches to check if your hardware design works correctly.

When simulating how your design behaves before making the actual hardware.

When you want to describe timing or delays only for simulation purposes.

When you need to print messages or debug information during simulation.

Syntax

VHDL

-- Synthesizable example
process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

-- Non-synthesizable example
process
begin
  wait for 10 ns;
  assert false report "Test message" severity note;
  wait;
end process;

Synthesizable code can be turned into hardware by synthesis tools.

Non-synthesizable code is used only during simulation and testing.

Examples

This is synthesizable code that describes a flip-flop triggered by a clock.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

This is non-synthesizable code used to wait and print a message during simulation only.

VHDL

process
begin
  wait for 10 ns;
  assert false report "Simulation message" severity note;
  wait;
end process;

Synthesizable code that counts clock cycles using a signal.

VHDL

signal temp : integer := 0;

process(clk)
begin
  if rising_edge(clk) then
    temp <= temp + 1;
  end if;
end process;

Non-synthesizable code to show messages at specific simulation times.

VHDL

process
begin
  report "Starting simulation";
  wait for 20 ns;
  report "Ending simulation";
  wait;
end process;

Sample Program

This VHDL code shows a synthesizable flip-flop that copies input d to output q on clock rising edge. It also has a non-synthesizable process that waits 10 ns and prints a message during simulation.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity example is
  port(
    clk : in std_logic;
    d : in std_logic;
    q : out std_logic
  );
end example;

architecture behavior of example is
begin
  -- Synthesizable process: flip-flop
  process(clk)
  begin
    if rising_edge(clk) then
      q <= d;
    end if;
  end process;

  -- Non-synthesizable process: simulation message
  process
  begin
    wait for 10 ns;
    report "Simulation started" severity note;
    wait;
  end process;
end behavior;

Important Notes

Only synthesizable constructs can be converted into hardware by synthesis tools.

Non-synthesizable constructs like 'wait for' or 'report' are ignored by synthesis but useful for simulation.

Always separate testbench code (non-synthesizable) from your hardware design code (synthesizable).

Summary

Synthesizable constructs describe real hardware behavior.

Non-synthesizable constructs help test and simulate but do not become hardware.

Use synthesizable code for design, non-synthesizable for simulation and debugging.

Practice

1. Which of the following VHDL constructs is synthesizable and can be implemented in hardware?

easy

A. Use of assert statements for debugging

B. A process containing wait for 10 ns; statements

C. File I/O operations like reading from a text file

D. A process with only clocked assignments and no wait statements

Solution

1. Step 1: Identify synthesizable constructs

   Synthesizable code must describe hardware behavior, typically using clocked processes without delays or waits.

2. Step 2: Analyze each option

   A process with only clocked assignments and no wait statements uses clocked assignments without waits, so it is synthesizable. Options A, B, and D use waits, assertions, or file I/O, which are non-synthesizable.

3. Final Answer:

   A process with only clocked assignments and no wait statements -> Option D

4. Quick Check:

   Synthesizable = clocked process without wait [OK]

Hint: Synthesizable means no waits or file I/O, just clocked logic [OK]

Common Mistakes:

• Thinking wait statements are synthesizable
• Confusing assert for hardware logic
• Assuming file I/O can be synthesized

2. Which VHDL syntax is not synthesizable?

easy

A. A process with a wait until clk = '1'; statement

B. Concurrent signal assignment outside any process

C. Signal assignment inside a clocked process

D. Using rising_edge(clk) inside a process

Solution

1. Step 1: Understand wait statement restrictions

   Wait statements like wait until clk = '1'; are not synthesizable because hardware cannot implement arbitrary waits.

2. Step 2: Check other options

   Options A, B, and C are standard synthesizable constructs: clock edge detection, signal assignments in processes, and concurrent assignments.

3. Final Answer:

   A process with a wait until clk = '1'; statement -> Option A

4. Quick Check:

   Wait statements = non-synthesizable [OK]

Hint: Wait statements inside processes are never synthesizable [OK]

Common Mistakes:

• Assuming wait until is synthesizable
• Confusing sensitivity list with wait statements
• Thinking concurrent assignments are non-synthesizable

3. What is the output behavior of this VHDL process when synthesized?

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. q synchronously resets to '0' on clock edge when reset is '1'

B. q asynchronously resets to '0' when reset is '1'

C. q changes immediately when reset is '1', ignoring clock

D. q never resets because reset is ignored

Solution

1. Step 1: Analyze reset behavior inside clocked process

   The reset check is inside the rising_edge(clk) condition, so reset is synchronous.

2. Step 2: Understand output assignment timing

   q is assigned '0' only on clock edge when reset is '1', otherwise q follows d on clock edges.

3. Final Answer:

   q synchronously resets to '0' on clock edge when reset is '1' -> Option A

4. Quick Check:

   Synchronous reset inside clock edge = q synchronously resets to '0' on clock edge when reset is '1' [OK]

Hint: Reset inside rising_edge means synchronous reset [OK]

Common Mistakes:

• Thinking reset is asynchronous here
• Assuming q changes immediately without clock
• Ignoring the rising_edge condition

4. Identify the error in this VHDL code snippet that prevents synthesis:

process(clk)
begin
  wait until clk = '1';
  q <= d;
end process;

medium

A. Signal assignment outside process

B. Missing sensitivity list in process

C. Using wait statement inside a clocked process

D. Incorrect use of <= operator

Solution

1. Step 1: Check for wait statement usage

   Wait statements inside processes are not synthesizable and cause synthesis errors.

2. Step 2: Verify other syntax elements

   The process has a sensitivity list (clk), signal assignment is inside process, and <= is correctly used.

3. Final Answer:

   Using wait statement inside a clocked process -> Option C

4. Quick Check:

   Wait inside process = synthesis error [OK]

Hint: Wait statements inside processes cause synthesis errors [OK]

Common Mistakes:

• Ignoring that wait is not synthesizable
• Confusing sensitivity list with wait usage
• Thinking <= operator is wrong here

5. You want to write a testbench to verify a VHDL design. Which construct is non-synthesizable but useful for simulation only?

hard

A. A clocked process with if rising_edge(clk) condition

B. A process with wait for 20 ns; to generate clock signals

C. Concurrent signal assignment for output signals

D. Signal assignment inside a synchronous reset process

Solution

1. Step 1: Identify testbench constructs

   Testbenches often use wait for statements to simulate timing delays, which are non-synthesizable.

2. Step 2: Compare with synthesizable constructs

   Options A, C, and D describe synthesizable hardware behavior, not simulation-only code.

3. Final Answer:

   A process with wait for 20 ns; to generate clock signals -> Option B

4. Quick Check:

   Wait for delays = simulation only [OK]

Hint: Use wait for delays only in testbenches, not hardware [OK]

Common Mistakes:

• Using wait for in synthesizable design code
• Confusing testbench and design code constructs
• Assuming clocked processes are non-synthesizable