Attribute usage for synthesis control in VHDL

Introduction

Attributes help guide the synthesis tool on how to handle parts of your VHDL code. They give extra instructions to make hardware behave as you want.

You want to tell the synthesis tool to keep a signal even if it looks unused.

You need to specify timing constraints or special hardware mapping for a signal or component.

You want to control optimization, like preventing a register from being merged.

You want to assign a specific pin location to a port in your design.

Syntax

VHDL

attribute attribute_name : attribute_type;
attribute attribute_name of object_name : entity is "value";

Attributes are declared first with their name and type.

Then you assign the attribute to a signal, variable, or entity with a value in quotes.

Examples

This tells the synthesis tool to keep my_signal even if it seems unused.

VHDL

attribute keep : boolean;
attribute keep of my_signal : signal is true;

This sets a maximum fanout of 4 for the clock signal clk.

VHDL

attribute max_fanout : integer;
attribute max_fanout of clk : signal is 4;

This assigns the physical pin P12 to the reset signal.

VHDL

attribute pin_location : string;
attribute pin_location of reset : signal is "P12";

Sample Program

This example shows how to use the keep attribute to tell the synthesis tool not to remove the temp signal, even if it looks unused. This helps keep the register in the hardware.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity example is
  port(
    clk : in std_logic;
    reset : in std_logic;
    data_in : in std_logic_vector(3 downto 0);
    data_out : out std_logic_vector(3 downto 0)
  );
end example;

architecture rtl of example is
  signal temp : std_logic_vector(3 downto 0);

  attribute keep : boolean;
  attribute keep of temp : signal is true;

begin
  process(clk, reset)
  begin
    if reset = '1' then
      temp <= (others => '0');
    elsif rising_edge(clk) then
      temp <= data_in;
    end if;
  end process;

  data_out <= temp;
end rtl;

Important Notes

Not all synthesis tools support all attributes; check your tool's documentation.

Attributes do not change simulation behavior, only synthesis.

Use attributes carefully to avoid unexpected hardware results.

Summary

Attributes give extra instructions to synthesis tools.

Declare attributes first, then assign them to signals or entities.

Common uses include keeping signals, setting pin locations, and controlling optimization.

Practice

1. What is the primary purpose of using attributes in VHDL synthesis control?

easy

A. To declare new signals in the design

B. To define the clock frequency of the design

C. To provide extra instructions to synthesis tools about signals or components

D. To write testbench stimulus

Solution

1. Step 1: Understand the role of attributes in VHDL

   Attributes are special metadata that give extra information to synthesis tools about how to treat signals or components.

2. Step 2: Differentiate attributes from other VHDL constructs

   Attributes do not declare signals or define clock frequencies; they provide instructions for synthesis optimization or constraints.

3. Final Answer:

   To provide extra instructions to synthesis tools about signals or components -> Option C

4. Quick Check:

   Attributes = extra synthesis instructions [OK]

Hint: Attributes give hints to synthesis tools, not declare signals [OK]

Common Mistakes:

• Confusing attributes with signal declarations
• Thinking attributes set clock frequencies
• Using attributes to write testbench code

2. Which of the following is the correct syntax to declare an attribute named keep_signal of type boolean in VHDL?

easy

A. attribute keep_signal : boolean is true;

B. attribute keep_signal : boolean;

C. attribute keep_signal : boolean := true;

D. attribute keep_signal : boolean := '1';

Solution

1. Step 1: Recall attribute declaration syntax

   Attributes are declared with the keyword attribute, followed by the name, colon, and type, ending with a semicolon.

2. Step 2: Identify correct syntax

   attribute keep_signal : boolean; matches the correct syntax: attribute keep_signal : boolean;. The other options incorrectly assign values or use invalid syntax.

3. Final Answer:

   attribute keep_signal : boolean; -> Option B

4. Quick Check:

   Declare attribute with name and type only [OK]

Hint: Declare attribute with name and type only, no value assigned [OK]

Common Mistakes:

• Assigning values during attribute declaration
• Using := instead of : for type declaration
• Using quotes for boolean type

3. Given the following VHDL code snippet, what is the effect of the attribute assignment?

attribute keep : boolean;
attribute keep of signal_a : signal is true;

medium

A. The signal signal_a will be preserved and not optimized away by synthesis

B. The signal signal_a will be removed during synthesis

C. The attribute has no effect on synthesis

D. The signal signal_a will be forced to zero

Solution

1. Step 1: Understand the attribute declaration and assignment

   The attribute keep is declared as boolean and assigned true to signal_a.

2. Step 2: Interpret the meaning of keep = true

   This instructs synthesis tools to preserve signal_a and not optimize it away, even if it seems unused.

3. Final Answer:

   The signal signal_a will be preserved and not optimized away by synthesis -> Option A

4. Quick Check:

   keep = true means preserve signal [OK]

Hint: Attribute keep=true means keep signal during synthesis [OK]

Common Mistakes:

• Assuming attribute removes the signal
• Thinking attribute forces signal value
• Ignoring attribute effect on synthesis

4. Identify the error in the following VHDL code related to attribute usage:

attribute keep : boolean;
attribute keep of signal_b : signal is 'true';

medium

A. The attribute value should not be in single quotes for boolean type

B. The attribute name cannot be the same as the signal name

C. The attribute must be declared after the signal

D. The attribute type should be integer, not boolean

Solution

1. Step 1: Check attribute value syntax

   The attribute keep is boolean, so its value should be true or false without quotes.

2. Step 2: Identify the error in value assignment

   Using single quotes around true makes it a character literal, which is invalid for boolean type.

3. Final Answer:

   The attribute value should not be in single quotes for boolean type -> Option A

4. Quick Check:

   Boolean attribute values are unquoted true/false [OK]

Hint: Boolean attribute values must be unquoted true or false [OK]

Common Mistakes:

• Putting boolean values in quotes
• Declaring attribute after signal
• Using wrong attribute type

5. You want to ensure a signal data_reg is not optimized away and also specify a maximum delay constraint using attributes. Which of the following is the correct way to declare and assign these attributes in VHDL?

hard

A. attribute keep : boolean;\nattribute max_delay : time;\nattribute keep of data_reg : signal is 'true';\nattribute max_delay of data_reg : signal is '10 ns';

B. attribute keep : boolean := true;\nattribute max_delay : time := 10 ns;\nattribute keep of data_reg : signal;\nattribute max_delay of data_reg : signal;

C. attribute keep : boolean;\nattribute max_delay : integer;\nattribute keep of data_reg : signal is 'true';\nattribute max_delay of data_reg : signal is 10;

D. attribute keep : boolean;\nattribute max_delay : time;\nattribute keep of data_reg : signal is true;\nattribute max_delay of data_reg : signal is 10 ns;

Solution

1. Step 1: Declare attributes with correct types

   Declare keep as boolean and max_delay as time type without assigning values during declaration.

2. Step 2: Assign attribute values correctly

   Assign keep as true (unquoted boolean) and max_delay as 10 ns (time literal) to data_reg.

3. Step 3: Verify syntax correctness

   attribute keep : boolean;\nattribute max_delay : time;\nattribute keep of data_reg : signal is true;\nattribute max_delay of data_reg : signal is 10 ns; matches correct syntax and value formats. Other options have errors like assigning values during declaration, wrong types, or quoting boolean/time literals.

4. Final Answer:

   attribute keep : boolean; attribute max_delay : time; attribute keep of data_reg : signal is true; attribute max_delay of data_reg : signal is 10 ns; -> Option D

5. Quick Check:

   Declare attributes then assign correct typed values [OK]

Hint: Declare attributes first, assign typed values without quotes [OK]

Common Mistakes:

• Assigning values during attribute declaration
• Using quotes around boolean or time values
• Using wrong attribute types