Configuration declaration in VHDL

Introduction

A configuration declaration in VHDL tells the computer which parts to use when building a circuit. It helps connect components and their implementations clearly.

When you have multiple versions of a component and want to choose which one to use.

When you want to specify exactly how components are connected in a design.

When you want to test different implementations without changing the main design.

When you want to organize large designs by controlling component bindings.

When you want to override default component bindings with specific ones.

Syntax

VHDL

configuration <configuration_name> of <entity_name> is
  for <architecture_name>
    for <component_name> : <component_entity>
      use entity <library_name>.<entity_name>(<architecture_name>);
    end for;
  end for;
end configuration <configuration_name>;

The configuration keyword starts the declaration.

You specify which entity and architecture this configuration applies to.

Examples

This example binds the component U1 inside MyCircuit to the Behavioral architecture of MyComponent.

VHDL

configuration MyConfig of MyCircuit is
  for Behavioral
    for U1 : MyComponent
      use entity work.MyComponent(Behavioral);
    end for;
  end for;
end configuration MyConfig;

This configuration uses the Optimized architecture of SubModule for the instance InstA inside TopEntity.

VHDL

configuration TestConfig of TopEntity is
  for RTL
    for InstA : SubModule
      use entity work.SubModule(Optimized);
    end for;
  end for;
end configuration TestConfig;

Sample Program

This program defines a circuit MyCircuit using a component MyComponent. The configuration MyConfig tells the circuit to use the Alternative architecture of MyComponent for the instance U1. So, the output b will be the NOT of input a.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity MyCircuit is
  port(
    a : in std_logic;
    b : out std_logic
  );
end entity MyCircuit;

architecture Behavioral of MyCircuit is
  component MyComponent
    port(
      x : in std_logic;
      y : out std_logic
    );
  end component;

  signal sig : std_logic;
begin
  U1: MyComponent port map(x => a, y => sig);
  b <= sig;
end Behavioral;

architecture Alternative of MyComponent is
begin
  y <= not x;
end Alternative;

architecture Behavioral of MyComponent is
begin
  y <= x;
end Behavioral;

configuration MyConfig of MyCircuit is
  for Behavioral
    for U1 : MyComponent
      use entity work.MyComponent(Alternative);
    end for;
  end for;
end configuration MyConfig;

Important Notes

Configuration declarations are optional but useful for controlling which component versions are used.

They help avoid changing the main design when switching implementations.

Make sure the configuration name matches the one used when simulating or synthesizing.

Summary

Configuration declarations select which component architectures to use in a design.

They help manage complex designs with multiple component versions.

Use configurations to easily switch implementations without changing main code.

Practice

1. What is the main purpose of a configuration declaration in VHDL?

easy

A. To specify timing constraints for simulation

B. To declare signals inside an architecture

C. To define new data types

D. To select which architecture is used for a component instance

Solution

1. Step 1: Understand the role of configuration declarations

   Configuration declarations in VHDL are used to specify which architecture should be bound to a component instance.

2. Step 2: Compare with other options

   Declaring signals, defining data types, or specifying timing constraints are done elsewhere, not in configurations.

3. Final Answer:

   To select which architecture is used for a component instance -> Option D

4. Quick Check:

   Configuration = Architecture selection [OK]

Hint: Configurations pick architectures for components quickly [OK]

Common Mistakes:

• Confusing configuration with signal declaration
• Thinking configuration defines data types
• Assuming configuration sets timing constraints

2. Which of the following is the correct syntax to start a configuration declaration in VHDL?

easy

A. configuration ConfigName for EntityName is

B. config ConfigName for EntityName begin

C. config ConfigName of EntityName begin

D. configuration ConfigName of EntityName is

Solution

1. Step 1: Recall VHDL configuration syntax

   The correct syntax starts with the keyword configuration, followed by the configuration name, then for, then the entity name, and ends with is.

2. Step 2: Match options with correct syntax

   configuration ConfigName for EntityName is matches exactly: configuration ConfigName for EntityName is. Others use incorrect keywords or order.

3. Final Answer:

   configuration ConfigName for EntityName is -> Option A

4. Quick Check:

   Syntax = configuration ... for ... is [OK]

Hint: Use 'configuration Name for Entity is' to start [OK]

Common Mistakes:

• Using 'of' instead of 'for'
• Omitting 'is' keyword
• Using 'config' instead of 'configuration'

3. Given the following VHDL configuration snippet:

configuration CFG1 for MyEntity is
  for ARCH1
    for U1: MyComponent
      use entity work.MyComponent(ARCH2);
    end for;
  end for;
end CFG1;

What architecture is used for the component instance U1 inside MyEntity when CFG1 is applied?

medium

A. ARCH1

B. MyEntity

C. ARCH2

D. work.MyComponent

Solution

1. Step 1: Analyze the configuration binding

   The configuration CFG1 binds the architecture ARCH1 to MyEntity. Inside ARCH1, the component instance U1 is explicitly bound to the architecture ARCH2 of MyComponent.

2. Step 2: Identify the architecture used for U1

   Because of the line use entity work.MyComponent(ARCH2);, U1 uses ARCH2, not ARCH1 or the entity name.

3. Final Answer:

   ARCH2 -> Option C

4. Quick Check:

   Instance U1 uses ARCH2 architecture [OK]

Hint: Look for 'use entity ... (ARCH)' inside configuration [OK]

Common Mistakes:

• Assuming U1 uses ARCH1 because of outer for
• Confusing entity name with architecture
• Ignoring nested 'use entity' clause

4. Identify the error in this VHDL configuration declaration:

configuration CFG2 for MyEntity is
  for ARCH1
    for U1: MyComponent
      use entity work.MyComponent(ARCH2)
    end for;
  end for;
end CFG2;

medium

A. Wrong keyword 'for' instead of 'of' in configuration header

B. Missing semicolon after 'use entity' statement

C. Component instance name 'U1' is invalid

D. Entity name 'MyEntity' is missing

Solution

1. Step 1: Check syntax of 'use entity' statement

   In VHDL configurations, each statement must end with a semicolon. The line use entity work.MyComponent(ARCH2) is missing a semicolon.

2. Step 2: Verify other parts

   The configuration header uses correct keywords, the instance name U1 is valid, and the entity name MyEntity is present.

3. Final Answer:

   Missing semicolon after 'use entity' statement -> Option B

4. Quick Check:

   Statements end with semicolon [OK]

Hint: Check semicolons after each statement in configuration [OK]

Common Mistakes:

• Omitting semicolon after 'use entity' line
• Confusing 'for' and 'of' keywords
• Assuming instance names must be uppercase

5. You have two architectures for an entity Processor: FastArch and SafeArch. You want to create a configuration that uses FastArch by default but switches to SafeArch for the component instance ALU inside Processor. Which configuration declaration correctly implements this?

hard

A. configuration CFG for Processor is
for FastArch
for ALU: ALUComponent
use entity work.ALUComponent(SafeArch);
end for;
end for;
end CFG;

B. configuration CFG for Processor is
for FastArch
for ALU: ALUComponent
use entity work.Processor(SafeArch);
end for;
end for;
end CFG;

C. configuration CFG for Processor is
for SafeArch
for ALU: ALUComponent
use entity work.ALUComponent(FastArch);
end for;
end for;
end CFG;

D. configuration CFG for Processor is
for FastArch
for ALU: Processor
use entity work.ALUComponent(SafeArch);
end for;
end for;
end CFG;

Solution

1. Step 1: Understand the requirement

   The configuration should use FastArch for Processor by default, but for the component instance ALU of type ALUComponent, it should use SafeArch.

2. Step 2: Check each option

   configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.ALUComponent(SafeArch); end for; end for; end CFG; correctly binds FastArch to Processor and overrides ALU instance to use SafeArch architecture of ALUComponent. configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.Processor(SafeArch); end for; end for; end CFG; incorrectly tries to bind SafeArch to Processor entity instead of ALUComponent. configuration CFG for Processor is for SafeArch for ALU: ALUComponent use entity work.ALUComponent(FastArch); end for; end for; end CFG; reverses the default and override. configuration CFG for Processor is for FastArch for ALU: Processor use entity work.ALUComponent(SafeArch); end for; end for; end CFG; incorrectly uses ALU instance as Processor type.

3. Final Answer:

   configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.ALUComponent(SafeArch); end for; end for; end CFG; -> Option A

4. Quick Check:

   Default architecture + instance override = configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.ALUComponent(SafeArch); end for; end for; end CFG; [OK]

Hint: Override instance architecture with 'use entity work.Component(Arch)' [OK]

Common Mistakes:

• Binding wrong entity in 'use entity' clause
• Swapping default and override architectures
• Using instance name as entity type