Port map association in VHDL

Introduction

Port map association connects parts of a design together so signals can flow between them.

When you want to connect a component inside a design to signals or other components.

When you build a bigger circuit from smaller parts and need to link their inputs and outputs.

When you want to reuse a component multiple times with different connections.

When you want to clearly show how signals connect to a component's ports.

Syntax

VHDL

component_name_instance : component_name port map (
    port1 => signal1,
    port2 => signal2,
    ...
);

Use => to connect each port of the component to a signal or expression.

The order of ports can be by name (recommended) or by position (less clear).

Examples

This connects the AND_GATE component ports A, B, and Y to signals input1, input2, and output.

VHDL

U1 : AND_GATE port map (
    A => input1,
    B => input2,
    Y => output
);

Associates the flip-flop ports to signals data_in, clock, and data_out.

VHDL

U2 : FLIP_FLOP port map (
    D => data_in,
    CLK => clock,
    Q => data_out
);

Sample Program

This program shows how to connect a simple AND gate component inside a top-level design using port map association. The signals input1 and input2 go into the AND gate, and the result is sent to output.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_and is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end simple_and;

architecture Behavioral of simple_and is
begin
    Y <= A and B;
end Behavioral;

entity top_level is
    Port ( input1 : in STD_LOGIC;
           input2 : in STD_LOGIC;
           output : out STD_LOGIC);
end top_level;

architecture Structural of top_level is
    component simple_and
        Port ( A : in STD_LOGIC;
               B : in STD_LOGIC;
               Y : out STD_LOGIC);
    end component;

    signal sig1, sig2, sig_out : STD_LOGIC;
begin
    -- Connect top-level inputs to internal signals
    sig1 <= input1;
    sig2 <= input2;

    -- Instantiate simple_and component and connect ports
    U1 : simple_and port map (
        A => sig1,
        B => sig2,
        Y => sig_out
    );

    -- Connect internal output signal to top-level output
    output <= sig_out;
end Structural;

Important Notes

Port map association uses the => symbol to clearly link ports to signals.

Using named association (port => signal) is clearer and safer than positional association.

Make sure the signal types match the port types to avoid errors.

Summary

Port map association links component ports to signals in your design.

Use named association with => for clarity.

This helps build bigger circuits from smaller parts.

Practice

1. What is the main purpose of port map in VHDL?

easy

A. To connect component ports to signals in the design

B. To declare new signals inside an architecture

C. To define the behavior of a component

D. To specify timing constraints for signals

Solution

1. Step 1: Understand the role of port map

   Port map is used to link the ports of a component to signals in the surrounding design.

2. Step 2: Differentiate from other VHDL constructs

   Declaring signals, defining behavior, or timing constraints are done elsewhere, not with port map.

3. Final Answer:

   To connect component ports to signals in the design -> Option A

4. Quick Check:

   Port map = connect ports to signals [OK]

Hint: Port map always links ports to signals by name [OK]

Common Mistakes:

• Confusing port map with signal declaration
• Thinking port map defines component behavior
• Mixing port map with timing constraints

2. Which of the following is the correct syntax for named port map association in VHDL?

easy

A. U1: component_name port map (clk : clk_signal, rst : reset_signal);

B. U1: component_name map port (clk = clk_signal, rst = reset_signal);

C. U1: component_name port map (clk => clk_signal, rst => reset_signal);

D. U1: component_name port map (clk <- clk_signal, rst <- reset_signal);

Solution

1. Step 1: Recall named association syntax

   Named port map uses the format port_name => signal_name inside parentheses.

2. Step 2: Check each option

   U1: component_name port map (clk => clk_signal, rst => reset_signal); uses => correctly. The other options use incorrect symbols (=, :, <-) for association.

3. Final Answer:

   U1: component_name port map (clk => clk_signal, rst => reset_signal); -> Option C

4. Quick Check:

   Named port map uses => [OK]

Hint: Use => for named port mapping in VHDL [OK]

Common Mistakes:

• Using = instead of => in port map
• Using : or <- instead of =>
• Omitting parentheses around port map list

3. Given the component declaration:

component AND_GATE
port(
  A : in std_logic;
  B : in std_logic;
  Y : out std_logic
);
end component;

And the following port map:

U1: AND_GATE port map (A => sig1, B => sig2, Y => out_sig);

What signal is connected to port B?

medium

A. sig1

B. B

C. out_sig

D. sig2

Solution

1. Step 1: Identify port map association for B

   In the port map, B is connected to sig2 as shown by B => sig2.

2. Step 2: Confirm signal connected to port B

   The signal connected to port B is sig2, not sig1 or out_sig.

3. Final Answer:

   sig2 -> Option D

4. Quick Check:

   Port B connected to sig2 [OK]

Hint: Match port name on left with signal on right in port map [OK]

Common Mistakes:

• Confusing port names with signal names
• Assuming order matters instead of names
• Selecting output signal instead of input

4. Identify the error in the following port map:

U2: MY_COMPONENT port map (clk => clock, reset => rst, data_in => input_data, data_out = output_data);

medium

A. Using '=' instead of '=>' for data_out association

B. Missing semicolon at the end of port map

C. Port names and signals are reversed

D. Component instance name 'U2' is invalid

Solution

1. Step 1: Check each port association syntax

   All associations use '=>' except data_out which uses '=' incorrectly.

2. Step 2: Verify other syntax elements

   Semicolon is present, port names and signals are correctly ordered, and instance name is valid.

3. Final Answer:

   Using '=' instead of '=>' for data_out association -> Option A

4. Quick Check:

   Port map uses =>, not = [OK]

Hint: All port associations must use =>, never = [OK]

Common Mistakes:

• Using = instead of => in one or more ports
• Confusing signal and port order
• Forgetting semicolon at end (not in this case)

5. You have a component with ports clk, rst, in_data, and out_data. You want to connect it to signals clk_sig, reset_sig, data_bus, and result_bus respectively. Which port map correctly associates these signals by name?

hard

A. U3: COMP port map (clk_sig => clk, reset_sig => rst, data_bus => in_data, result_bus => out_data);

B. U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus);

C. U3: COMP port map (clk => reset_sig, rst => clk_sig, in_data => result_bus, out_data => data_bus);

D. U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => result_bus, out_data => data_bus);

Solution

1. Step 1: Match each port to its correct signal

   Ports clk, rst, in_data, out_data must connect to clk_sig, reset_sig, data_bus, result_bus respectively.

2. Step 2: Check each option's mapping

   U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus); correctly maps each port to its matching signal. The other options swap signals incorrectly.

3. Final Answer:

   U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus); -> Option B

4. Quick Check:

   Port to signal mapping must be exact [OK]

Hint: Port name on left, signal on right in port map [OK]

Common Mistakes:

• Swapping signal names in port map
• Reversing port and signal positions
• Mixing input and output signals