SPI master controller in VHDL

Introduction

An SPI master controller manages communication with SPI devices by sending and receiving data bits in a timed sequence. It controls the clock and data lines to talk to other devices.

When you want to control sensors or memory chips that use SPI communication.

When you need to send commands and receive data from SPI peripherals like displays or ADCs.

When designing embedded systems that require fast, synchronous data exchange.

When you want to implement a custom SPI interface in an FPGA or CPLD.

When you need precise control over SPI timing and data flow.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity spi_master is
    port(
        clk       : in  std_logic;
        reset     : in  std_logic;
        mosi      : out std_logic;
        miso      : in  std_logic;
        sclk      : out std_logic;
        cs        : out std_logic;
        data_in   : in  std_logic_vector(7 downto 0);
        data_out  : out std_logic_vector(7 downto 0);
        start     : in  std_logic;
        done      : out std_logic
    );
end spi_master;

architecture Behavioral of spi_master is
    -- internal signals and state machine here
begin
    -- SPI logic here
end Behavioral;

The clk is the system clock driving the SPI controller.

mosi sends data to the slave, miso receives data from the slave.

Examples

This defines the SPI master interface with clock, reset, data lines, and control signals.

VHDL

entity spi_master is
    port(
        clk       : in  std_logic;
        reset     : in  std_logic;
        mosi      : out std_logic;
        miso      : in  std_logic;
        sclk      : out std_logic;
        cs        : out std_logic;
        data_in   : in  std_logic_vector(7 downto 0);
        data_out  : out std_logic_vector(7 downto 0);
        start     : in  std_logic;
        done      : out std_logic
    );
end spi_master;

This is a simple state machine that controls SPI data transfer bit by bit.

VHDL

architecture Behavioral of spi_master is
    type state_type is (idle, transfer, finish);
    signal state : state_type := idle;
    signal bit_count : integer range 0 to 7 := 0;
    signal shift_reg : std_logic_vector(7 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= idle;
            bit_count <= 0;
            sclk <= '0';
            cs <= '1';
            done <= '0';
        elsif rising_edge(clk) then
            case state is
                when idle =>
                    if start = '1' then
                        cs <= '0';
                        shift_reg <= data_in;
                        bit_count <= 7;
                        state <= transfer;
                        done <= '0';
                    end if;
                when transfer =>
                    sclk <= not sclk;
                    if sclk = '0' then
                        mosi <= shift_reg(bit_count);
                    else
                        shift_reg(bit_count) <= miso;
                        if bit_count = 0 then
                            state <= finish;
                        else
                            bit_count <= bit_count - 1;
                        end if;
                    end if;
                when finish =>
                    cs <= '1';
                    data_out <= shift_reg;
                    done <= '1';
                    state <= idle;
            end case;
        end if;
    end process;
end Behavioral;

Sample Program

This complete SPI master controller sends 8 bits from data_in to the slave and reads 8 bits back on miso. It uses a simple state machine with start and done signals.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity spi_master is
    port(
        clk       : in  std_logic;
        reset     : in  std_logic;
        mosi      : out std_logic;
        miso      : in  std_logic;
        sclk      : out std_logic;
        cs        : out std_logic;
        data_in   : in  std_logic_vector(7 downto 0);
        data_out  : out std_logic_vector(7 downto 0);
        start     : in  std_logic;
        done      : out std_logic
    );
end spi_master;

architecture Behavioral of spi_master is
    type state_type is (idle, transfer, finish);
    signal state : state_type := idle;
    signal bit_count : integer range 0 to 7 := 7;
    signal shift_reg : std_logic_vector(7 downto 0) := (others => '0');
    signal sclk_reg : std_logic := '0';
    signal mosi_reg : std_logic := '0';
begin
    sclk <= sclk_reg;
    mosi <= mosi_reg;

    process(clk, reset)
    begin
        if reset = '1' then
            state <= idle;
            bit_count <= 7;
            sclk_reg <= '0';
            cs <= '1';
            done <= '0';
            mosi_reg <= '0';
            data_out <= (others => '0');
            shift_reg <= (others => '0');
        elsif rising_edge(clk) then
            case state is
                when idle =>
                    done <= '0';
                    sclk_reg <= '0';
                    cs <= '1';
                    if start = '1' then
                        cs <= '0';
                        shift_reg <= data_in;
                        bit_count <= 7;
                        state <= transfer;
                    end if;
                when transfer =>
                    sclk_reg <= not sclk_reg;
                    if sclk_reg = '0' then
                        mosi_reg <= shift_reg(bit_count);
                    else
                        shift_reg(bit_count) <= miso;
                        if bit_count = 0 then
                            state <= finish;
                        else
                            bit_count <= bit_count - 1;
                        end if;
                    end if;
                when finish =>
                    cs <= '1';
                    data_out <= shift_reg;
                    done <= '1';
                    state <= idle;
            end case;
        end if;
    end process;
end Behavioral;

Important Notes

SPI clock polarity and phase are not handled here; this example assumes mode 0 (CPOL=0, CPHA=0).

The cs signal is active low and controls the slave selection.

Make sure the system clock is fast enough to generate the SPI clock by toggling sclk.

Summary

An SPI master controller manages data transfer by controlling clock and data lines.

It uses a state machine to send and receive bits one by one.

Signals like start and done help coordinate the transfer process.

Practice

1. What is the primary role of the SPI master controller in VHDL designs?

easy

A. To convert SPI signals into parallel data only

B. To act as a slave device responding to SPI commands

C. To generate random data for SPI devices

D. To control the clock, chip select, and data lines for SPI communication

Solution

1. Step 1: Understand SPI roles

   The SPI master controls communication timing and signals like clock and chip select.

2. Step 2: Identify controller function

   The master sends and receives data by managing these lines, unlike a slave which only responds.

3. Final Answer:

   To control the clock, chip select, and data lines for SPI communication -> Option D

4. Quick Check:

   SPI master controls clock, chip select, data lines [OK]

Hint: Master controls clock and chip select lines [OK]

Common Mistakes:

• Confusing master with slave device
• Thinking master only sends data without control
• Assuming master generates random data

2. Which VHDL statement correctly declares a 8-bit shift register signal for SPI data?

easy

A. signal shift_reg : integer range 0 to 255;

B. signal shift_reg : std_logic_vector(7 downto 0);

C. signal shift_reg : std_logic;

D. signal shift_reg : bit_vector(0 to 7);

Solution

1. Step 1: Identify correct data type for shift register

   Shift registers for SPI data use std_logic_vector for bit-wise operations.

2. Step 2: Check syntax and range

   std_logic_vector(7 downto 0) correctly defines 8 bits from MSB to LSB.

3. Final Answer:

   signal shift_reg : std_logic_vector(7 downto 0); -> Option B

4. Quick Check:

   Use std_logic_vector(7 downto 0) for 8-bit register [OK]

Hint: Use std_logic_vector with downto for bit vectors [OK]

Common Mistakes:

• Using integer instead of bit vector
• Using bit_vector which is less common
• Declaring single bit instead of vector

3. Given this VHDL process snippet for SPI clock generation:

process(clk)
begin
  if rising_edge(clk) then
    if clk_div = 1 then
      spi_clk <= not spi_clk;
      clk_div <= 0;
    else
      clk_div <= clk_div + 1;
    end if;
  end if;
end process;

What is the frequency relationship between spi_clk and clk?

medium

A. spi_clk frequency equals clk frequency

B. spi_clk frequency is double clk frequency

C. spi_clk frequency is half of clk frequency

D. spi_clk frequency is unrelated to clk frequency

Solution

1. Step 1: Analyze clock division logic

   clk_div toggles spi_clk every 2 rising edges of clk, flipping spi_clk once per two clk cycles.

2. Step 2: Determine frequency ratio

   Since spi_clk toggles every 2 clk cycles, its frequency is half of clk frequency.

3. Final Answer:

   spi_clk frequency is half of clk frequency -> Option C

4. Quick Check:

   spi_clk toggles every 2 clk cycles = half frequency [OK]

Hint: Toggle output every 2 input cycles halves frequency [OK]

Common Mistakes:

• Assuming frequencies are equal
• Thinking frequency doubles
• Ignoring clk_div counter effect

4. Identify the error in this SPI master controller state machine snippet:

type state_type is (IDLE, LOAD, TRANSFER);
signal state : state_type := IDLE;

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        if start = '1' then
          state <= LOAD;
        end if;
      when LOAD =>
        state <= TRANSFER;
      when TRANSFER =>
        if bit_count = 8 then
          state <= IDLE;
        end if;
    end case;
  end if;
end process;

medium

A. bit_count is not reset, causing TRANSFER to never end

B. Missing default case in state machine

C. start signal is not checked in TRANSFER state

D. State transitions are missing LOAD to IDLE path

Solution

1. Step 1: Check state transitions and counters

   TRANSFER state depends on bit_count reaching 8 to return to IDLE.

2. Step 2: Identify missing reset of bit_count

   If bit_count is never reset to 0, it may never reach 8, so TRANSFER state loops indefinitely.

3. Final Answer:

   bit_count is not reset, causing TRANSFER to never end -> Option A

4. Quick Check:

   bit_count reset missing = infinite TRANSFER [OK]

Hint: Always reset counters to avoid infinite states [OK]

Common Mistakes:

• Ignoring counter reset logic
• Expecting default case is mandatory
• Confusing start signal usage

5. You want to extend an SPI master controller to support variable data widths (4 to 16 bits). Which VHDL approach best handles this requirement?

hard

A. Use a generic parameter for data width and adjust shift register size accordingly

B. Hardcode shift register to 16 bits and ignore unused bits

C. Create separate modules for each data width and select at compile time

D. Use integer counters only without shift registers

Solution

1. Step 1: Understand variable data width needs

   Supporting 4 to 16 bits requires flexible register size and control logic.

2. Step 2: Use generics for flexibility

   Generics allow parameterizing data width at compile time, adjusting shift register size dynamically.

3. Step 3: Evaluate other options

   Hardcoding wastes resources; separate modules increase complexity; counters alone can't shift data.

4. Final Answer:

   Use a generic parameter for data width and adjust shift register size accordingly -> Option A

5. Quick Check:

   Generics enable flexible data width in VHDL [OK]

Hint: Use generics to set data width flexibly [OK]

Common Mistakes:

• Hardcoding fixed sizes wastes resources
• Creating many modules complicates design
• Ignoring shift register role in data transfer