UART transmitter and receiver in VHDL

Introduction

UART lets two devices talk by sending data one bit at a time. The transmitter sends data, and the receiver gets it.

When you want to send text from a microcontroller to a computer.

When two chips need to exchange small amounts of data without wires for many signals.

When you want to connect sensors or modules that use serial communication.

When debugging embedded systems by sending messages to a PC.

When building simple wireless or wired communication between devices.

Syntax

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity uart_tx is
  Port (
    clk       : in  std_logic;
    reset     : in  std_logic;
    tx_start  : in  std_logic;
    tx_data   : in  std_logic_vector(7 downto 0);
    tx_serial : out std_logic;
    tx_busy   : out std_logic
  );
end uart_tx;

architecture Behavioral of uart_tx is
  -- internal signals and states
begin
  -- process to handle transmission
end Behavioral;

This is a basic structure for a UART transmitter in VHDL.

Receiver has a similar structure but reads bits instead of sending.

Examples

This is the entity for a UART receiver. It listens to serial data and outputs bytes.

VHDL

entity uart_rx is
  Port (
    clk       : in  std_logic;
    reset     : in  std_logic;
    rx_serial : in  std_logic;
    rx_data   : out std_logic_vector(7 downto 0);
    rx_ready  : out std_logic
  );
end uart_rx;

This shows states and signals used to send bits step by step.

VHDL

architecture Behavioral of uart_tx is
  type state_type is (idle, start_bit, data_bits, stop_bit);
  signal state : state_type := idle;
  signal bit_count : integer range 0 to 7 := 0;
  signal shift_reg : std_logic_vector(7 downto 0) := (others => '0');
begin
  -- process to send bits one by one
end Behavioral;

Sample Program

This UART transmitter sends 8 bits serially with start and stop bits. It uses a simple state machine to control sending bits.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity uart_tx is
  Port (
    clk       : in  std_logic;
    reset     : in  std_logic;
    tx_start  : in  std_logic;
    tx_data   : in  std_logic_vector(7 downto 0);
    tx_serial : out std_logic;
    tx_busy   : out std_logic
  );
end uart_tx;

architecture Behavioral of uart_tx is
  type state_type is (idle, start_bit, data_bits, stop_bit);
  signal state : state_type := idle;
  signal bit_count : integer range 0 to 7 := 0;
  signal shift_reg : std_logic_vector(7 downto 0) := (others => '0');
  signal tx_line : std_logic := '1';
begin
  tx_serial <= tx_line;
  tx_busy <= '1' when state /= idle else '0';

  process(clk, reset)
  begin
    if reset = '1' then
      state <= idle;
      tx_line <= '1';
      bit_count <= 0;
      shift_reg <= (others => '0');
    elsif rising_edge(clk) then
      case state is
        when idle =>
          tx_line <= '1';
          if tx_start = '1' then
            shift_reg <= tx_data;
            state <= start_bit;
          end if;
        when start_bit =>
          tx_line <= '0'; -- start bit is low
          state <= data_bits;
          bit_count <= 0;
        when data_bits =>
          tx_line <= shift_reg(bit_count);
          if bit_count = 7 then
            state <= stop_bit;
          else
            bit_count <= bit_count + 1;
          end if;
        when stop_bit =>
          tx_line <= '1'; -- stop bit is high
          state <= idle;
        when others =>
          state <= idle;
      end case;
    end if;
  end process;
end Behavioral;

Important Notes

UART needs a shared speed (baud rate) between sender and receiver to work correctly.

Start bit is always low, stop bit is always high to mark data boundaries.

In real designs, a baud rate generator is used to time bits precisely.

Summary

UART sends data bit by bit using start and stop bits.

Transmitter and receiver use state machines to handle bits.

VHDL code models this behavior with signals and processes.

Practice

1. What is the main role of the UART transmitter in a communication system?

easy

A. To send data bits serially with start and stop bits

B. To receive data bits and convert them to parallel form

C. To amplify the signal strength for transmission

D. To encrypt data before sending

Solution

1. Step 1: Understand UART transmitter function

   The UART transmitter converts parallel data into serial form and adds start and stop bits for synchronization.

2. Step 2: Differentiate transmitter from receiver roles

   The receiver listens and converts serial data back to parallel, so amplification or encryption is not the transmitter's main role.

3. Final Answer:

   To send data bits serially with start and stop bits -> Option A

4. Quick Check:

   Transmitter sends serial data = A [OK]

Hint: Remember: transmitter sends serial bits with start/stop [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking transmitter encrypts data
• Assuming transmitter amplifies signals

2. Which of the following is the correct VHDL port declaration for a UART receiver input line named rx?

easy

A. rx : out std_logic;

B. rx : inout std_logic_vector(7 downto 0);

C. rx : in std_logic;

D. rx : buffer std_logic_vector(7 downto 0);

Solution

1. Step 1: Identify direction of UART receiver input

   The receiver reads data from the input line, so the port direction must be 'in'.

2. Step 2: Check data type for single UART line

   UART input is a single bit line, so type is std_logic, not a vector.

3. Final Answer:

   rx : in std_logic; -> Option C

4. Quick Check:

   Receiver input is 'in std_logic' = C [OK]

Hint: Input lines use 'in std_logic' for single UART signals [OK]

Common Mistakes:

• Using 'out' instead of 'in' for receiver input
• Using std_logic_vector for single bit line
• Using 'buffer' or 'inout' incorrectly

3. Given this VHDL snippet for a UART transmitter process, what is the value of tx_line after sending the start bit?

process(clk)
begin
  if rising_edge(clk) then
    if state = IDLE then
      tx_line <= '1';
    elsif state = START_BIT then
      tx_line <= '0';
    end if;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. 'X'

Solution

1. Step 1: Analyze process behavior at START_BIT state

   When state equals START_BIT, the code sets tx_line to '0', representing the start bit.

2. Step 2: Confirm output value after start bit

   Since the start bit is '0', tx_line will be '0' during START_BIT state.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Start bit = '0' on tx_line = B [OK]

Hint: Start bit in UART is always '0' on tx_line [OK]

Common Mistakes:

• Confusing start bit with idle line '1'
• Assuming 'Z' or 'X' values appear
• Ignoring state conditions

4. Identify the error in this UART receiver process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if rx = '0' then
      data <= rx_data & rx;
    end if;
  end if;
end process;

medium

A. Missing reset condition for data register

B. Concatenation order is incorrect for data assembly

C. rx signal should be '1' to detect start bit

D. Process sensitivity list is incomplete

Solution

1. Step 1: Check process for reset handling

   The process lacks a reset condition to clear or initialize 'data', which is essential for reliable UART reception.

2. Step 2: Validate other parts

   Concatenation order and rx = '0' for start bit detection are correct; sensitivity list with clk is standard.

3. Final Answer:

   Missing reset condition for data register -> Option A

4. Quick Check:

   Reset needed to clear data = A [OK]

Hint: Always include reset in UART receiver process [OK]

Common Mistakes:

• Ignoring reset causes data corruption
• Thinking start bit is '1'
• Misunderstanding concatenation order

5. You want to design a UART transmitter in VHDL that sends 8-bit data with 1 start bit, 1 stop bit, and no parity. Which sequence correctly represents the bits sent on the tx line for data byte "10110011"?

hard

A. Start bit '0', data bits MSB first '10110011', stop bit '1'

B. Start bit '1', data bits MSB first '10110011', stop bit '0'

C. Start bit '0', data bits LSB first '11001101', stop bit '0'

D. Start bit '0', data bits LSB first '11001101', stop bit '1'

Solution

1. Step 1: Recall UART bit order and framing

   UART sends a start bit '0', then data bits least significant bit (LSB) first, then stop bit '1'.

2. Step 2: Convert data byte to LSB first sequence

   Data '10110011' MSB to LSB is bits 7 to 0. LSB first means sending '11001101'.

3. Step 3: Confirm start and stop bits

   Start bit is '0', stop bit is '1' as per UART standard.

4. Final Answer:

   Start bit '0', data bits LSB first '11001101', stop bit '1' -> Option D

5. Quick Check:

   UART sends start '0', LSB first, stop '1' = D [OK]

Hint: UART sends LSB first with start '0' and stop '1' bits [OK]

Common Mistakes:

• Sending MSB first instead of LSB first
• Using wrong stop bit value
• Confusing start bit as '1'