Clock divider with enable in VHDL

Introduction

A clock divider with enable helps slow down a fast clock signal to a slower one, but only when you want it to work.

You want to blink an LED slower than the main clock speed.

You need to create a slower timing signal for other parts of your circuit.

You want to save power by only running the slower clock when needed.

You want to control when the slower clock runs using a switch or signal.

Syntax

VHDL

process(clk, reset)
begin
  if reset = '1' then
    counter <= 0;
    slow_clk <= '0';
  elsif rising_edge(clk) then
    if enable = '1' then
      if counter = DIVIDE_VALUE then
        slow_clk <= not slow_clk;
        counter <= 0;
      else
        counter <= counter + 1;
      end if;
    end if;
  end if;
end process;

The process runs on the main clock and reset signals.

The enable signal controls if the clock divider counts or not.

Examples

Only count when enable is high.

VHDL

if enable = '1' then
  counter <= counter + 1;
end if;

Toggle the slow clock every 5 counts (0 to 4).

VHDL

if counter = 4 then
  slow_clk <= not slow_clk;
  counter <= 0;
end if;

Sample Program

This VHDL code creates a clock divider that toggles the output clock every 5 input clock cycles, but only when enable is high. Reset sets everything back to zero.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_divider_enable is
  port(
    clk     : in std_logic;
    reset   : in std_logic;
    enable  : in std_logic;
    slow_clk: out std_logic
  );
end clock_divider_enable;

architecture Behavioral of clock_divider_enable is
  constant DIVIDE_VALUE : integer := 4;
  signal counter : integer range 0 to DIVIDE_VALUE := 0;
  signal slow_clk_int : std_logic := '0';
begin
  process(clk, reset)
  begin
    if reset = '1' then
      counter <= 0;
      slow_clk_int <= '0';
    elsif rising_edge(clk) then
      if enable = '1' then
        if counter = DIVIDE_VALUE then
          slow_clk_int <= not slow_clk_int;
          counter <= 0;
        else
          counter <= counter + 1;
        end if;
      end if;
    end if;
  end process;

  slow_clk <= slow_clk_int;
end Behavioral;

Important Notes

The output clock frequency is the input clock frequency divided by 2 * (DIVIDE_VALUE + 1).

If enable is low, the output clock stays the same and the counter does not count.

Resetting sets the output clock to '0' and counter to zero immediately.

Summary

A clock divider with enable slows down a clock only when enabled.

Use a counter to count input clock cycles and toggle output clock.

Reset clears the counter and output clock to start fresh.

Practice

1. What is the main purpose of a clock divider with enable in VHDL?

easy

A. To reset the clock signal automatically

B. To increase the clock frequency permanently

C. To generate a random clock signal

D. To slow down the clock signal only when the enable is active

Solution

1. Step 1: Understand clock divider function

   A clock divider reduces the frequency of the input clock signal.

2. Step 2: Role of enable signal

   The enable signal controls when the clock divider is active, so it only slows the clock when enabled.

3. Final Answer:

   To slow down the clock signal only when the enable is active -> Option D

4. Quick Check:

   Clock divider + enable = slow clock only if enabled [OK]

Hint: Enable controls when clock slows down [OK]

Common Mistakes:

• Thinking clock always slows down regardless of enable
• Confusing enable with reset
• Assuming clock frequency increases

2. Which of the following is the correct VHDL syntax to declare an enable input signal in an entity?

easy

A. enable : in std_logic;

B. enable : out std_logic;

C. enable : in integer;

D. enable : buffer std_logic;

Solution

1. Step 1: Identify signal direction for enable

   Enable is an input signal, so direction must be 'in'.

2. Step 2: Identify signal type for enable

   Enable is usually a single bit signal, so type is 'std_logic'.

3. Final Answer:

   enable : in std_logic; -> Option A

4. Quick Check:

   Enable input signal = in std_logic [OK]

Hint: Enable is input, so use 'in std_logic' [OK]

Common Mistakes:

• Using 'out' instead of 'in' for enable
• Using integer type for enable
• Using 'buffer' incorrectly

3. Given this VHDL process snippet for a clock divider with enable:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    clk_out <= '0';
  elsif rising_edge(clk) then
    if enable = '1' then
      if count = 3 then
        clk_out <= not clk_out;
        count <= 0;
      else
        count <= count + 1;
      end if;
    end if;
  end if;
end process;

What is the frequency division factor of clk_out relative to clk when enabled?

medium

A. 4

B. 2

C. 8

D. 3

Solution

1. Step 1: Understand counting and toggling

   The counter counts from 0 to 3 (4 counts). When count=3, clk_out toggles.

2. Step 2: Calculate division factor

   Each toggle happens every 4 clock cycles, so full clk_out period is 8 clk cycles (toggle twice for full cycle).

3. Final Answer:

   8 -> Option C

4. Quick Check:

   Toggle every 4 cycles -> divide by 8 frequency [OK]

Hint: Toggle output every 4 cycles means divide by 8 [OK]

Common Mistakes:

• Confusing toggle count with division factor
• Counting only half the period
• Ignoring enable condition

4. Identify the error in this VHDL clock divider process with enable:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    clk_out <= '0';
  elsif rising_edge(clk) then
    if enable = '1' then
      if count = 4 then
        clk_out <= not clk_out;
        count <= 0;
      else
        count <= count + 1;
      end if;
    end if;
  end if;
end process;

What is the main problem?

medium

A. Missing else clause for enable = '0'

B. Counter compares to 4 but counts from 0, causing off-by-one error

C. clk_out toggles on falling edge instead of rising edge

D. Reset condition is inside rising_edge(clk) block

Solution

1. Step 1: Check counter comparison

   Counter counts from 0 upwards, but compares to 4, so counts 0 to 4 (5 counts).

2. Step 2: Identify off-by-one error

   Usually counter should compare to max count minus 1 (3 for 4 counts), so this causes timing error.

3. Final Answer:

   Counter compares to 4 but counts from 0, causing off-by-one error -> Option B

4. Quick Check:

   Count 0 to 4 means 5 counts, off-by-one [OK]

Hint: Count from 0 means max compare is count-1 [OK]

Common Mistakes:

• Thinking enable needs else clause
• Confusing reset placement
• Misreading edge sensitivity

5. You want to design a clock divider with enable that divides the input clock by 10 only when enabled. Which approach correctly implements this in VHDL?

hard

A. Use a 5-bit counter counting 0 to 4, toggle output on count=4, increment counter only if enable='1'

B. Use a 3-bit counter counting 0 to 4, toggle output on count=4, ignore enable signal

C. Use a 4-bit counter counting 0 to 10, toggle output on count=10, reset counter on reset only

D. Use a 4-bit counter counting 0 to 9, toggle output on count=9, reset counter on enable='0'

Solution

1. Step 1: Determine counter size and range

   Dividing by 10 requires counting 5 clock cycles (0 to 4), so 3 bits are enough but 5 bits also work safely.

2. Step 2: Control counter with enable

   Counter should increment only when enable='1' to slow clock only when enabled.

3. Step 3: Toggle output on max count

   Toggle output clock when count reaches 4, then reset counter to 0.

4. Final Answer:

   Use a 5-bit counter counting 0 to 4, toggle output on count=4, increment counter only if enable='1' -> Option A

5. Quick Check:

   Count 0-4 + enable control = correct divider [OK]

Hint: Increment counter only when enabled for correct division [OK]

Common Mistakes:

• Ignoring enable signal in counter increment
• Counting wrong range causing wrong division
• Resetting counter on enable='0' instead of pause