Watchdog timer design in VHDL - Time & Space Complexity

Time Complexity: Watchdog timer design

O(n)

Understanding Time Complexity

We want to understand how the time it takes for a watchdog timer to operate changes as its input size grows.

Specifically, we ask: how does the number of steps the timer takes grow when the timer counts higher?

Scenario Under Consideration

Analyze the time complexity of the following VHDL watchdog timer process.

process(clk, reset)
begin
  if reset = '1' then
    counter <= 0;
  elsif rising_edge(clk) then
    if counter < MAX_COUNT then
      counter <= counter + 1;
    else
      timeout <= '1';
    end if;
  end if;
end process;

This code counts clock pulses until it reaches a maximum count, then signals a timeout.

Identify Repeating Operations

Look for loops or repeated steps in the code.

• Primary operation: Incrementing the counter on each clock pulse.
• How many times: Up to MAX_COUNT times before timeout triggers.

How Execution Grows With Input

The number of increments grows directly with MAX_COUNT.

Input Size (MAX_COUNT)	Approx. Operations (increments)
10	10
100	100
1000	1000

Pattern observation: The steps increase in a straight line as MAX_COUNT grows.

Final Time Complexity

Time Complexity: O(n)

This means the time to reach timeout grows directly in proportion to the maximum count value.

Common Mistake

[X] Wrong: "The timer triggers instantly regardless of MAX_COUNT."

[OK] Correct: The timer must count each clock pulse up to MAX_COUNT, so it takes longer for bigger counts.

Interview Connect

Understanding how counting loops grow with input size helps you explain timing and delays in hardware design clearly and confidently.

Self-Check

"What if we changed the counter to increment by 2 each clock instead of 1? How would the time complexity change?"

Practice

1. What is the main purpose of a watchdog timer in a VHDL design?

easy

A. To generate random numbers for encryption

B. To increase the clock speed of the system

C. To store data temporarily during processing

D. To detect system failures and trigger a reset if the system stops responding

Solution

1. Step 1: Understand the watchdog timer role

   A watchdog timer monitors system activity to detect failures.

2. Step 2: Identify the correct function

   It triggers a reset if the system stops responding to prevent lockup.

3. Final Answer:

   To detect system failures and trigger a reset if the system stops responding -> Option D

4. Quick Check:

   Watchdog timer = system failure detection [OK]

Hint: Watchdog timer resets system on failure detection [OK]

Common Mistakes:

• Confusing watchdog timer with clock generator
• Thinking it stores data
• Assuming it generates random numbers

2. Which of the following is the correct VHDL signal declaration for a 16-bit counter used in a watchdog timer?

easy

A. signal counter : std_logic_vector(15 downto 0);

B. signal counter : integer range 0 to 15;

C. signal counter : std_logic_vector(0 to 15);

D. signal counter : bit_vector(16 downto 1);

Solution

1. Step 1: Identify correct vector size and direction

   A 16-bit vector uses indices 15 downto 0 for standard logic vectors.

2. Step 2: Check each option

   signal counter : std_logic_vector(15 downto 0); uses std_logic_vector(15 downto 0), which is correct for 16 bits.

3. Final Answer:

   signal counter : std_logic_vector(15 downto 0); -> Option A

4. Quick Check:

   16-bit vector = (15 downto 0) [OK]

Hint: Use downto for descending bit ranges in vectors [OK]

Common Mistakes:

• Using integer range 0 to 15 instead of vector
• Using ascending range (0 to 15) incorrectly
• Using bit_vector instead of std_logic_vector

3. Given this VHDL process snippet for a watchdog timer counter:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What happens to counter when kick is '1'?

medium

A. Counter resets to zero

B. Counter increments by one

C. Counter holds its current value

D. Counter resets to all ones

Solution

1. Step 1: Analyze the condition when kick = '1'

   The code sets counter to (others => '0'), which means all bits zero.

2. Step 2: Understand the effect on counter

   Counter resets to zero instead of incrementing.

3. Final Answer:

   Counter resets to zero -> Option A

4. Quick Check:

   kick '1' resets counter = zero [OK]

Hint: kick '1' means reset counter to zero [OK]

Common Mistakes:

• Assuming counter increments on kick
• Thinking counter holds value on kick
• Confusing reset value with all ones

4. Identify the error in this VHDL watchdog timer process:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using rising_edge(clk) incorrectly

B. Assigning integer 0 to a std_logic_vector signal

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check signal type and assignment

   Counter is usually std_logic_vector; assigning integer 0 directly is invalid.

2. Step 2: Identify correct assignment method

   Must assign (others => '0') or convert integer to vector properly.

3. Final Answer:

   Assigning integer 0 to a std_logic_vector signal -> Option B

4. Quick Check:

   std_logic_vector needs vector assignment, not integer [OK]

Hint: Assign vectors with (others=>'0'), not integer 0 [OK]

Common Mistakes:

• Assigning integer directly to vector
• Ignoring reset conditions
• Misusing clock edge detection

5. You want to design a watchdog timer in VHDL that triggers a timeout signal when the counter reaches 1000 without a kick. Which approach correctly implements this behavior?

hard

A. Increment counter only when kick = '1'; reset counter when timeout = '1'; set timeout when counter > 1000

B. Reset counter on timeout; increment counter only when kick = '1'; set timeout when counter = 1000

C. Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000

D. Set timeout to '1' every clock cycle; reset counter only when kick = '0'

Solution

1. Step 1: Understand watchdog timer logic

   Counter increments every clock cycle unless reset by kick signal.

2. Step 2: Identify correct timeout condition

   Timeout triggers when counter reaches 1000 without reset.

3. Step 3: Evaluate options

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 matches correct logic: increment, reset on kick, timeout at 1000.

4. Final Answer:

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 -> Option C

5. Quick Check:

   Watchdog counts up, resets on kick, timeout at limit [OK]

Hint: Count up, reset on kick, timeout at limit [OK]

Common Mistakes:

• Incrementing only on kick
• Setting timeout every cycle
• Resetting counter incorrectly