0A watchdog timer helps a digital system check if it is working properly. If the system stops responding, the watchdog timer resets it to fix the problem.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity watchdog_timer is port( clk : in std_logic; reset_n : in std_logic; kick : in std_logic; -- signal to reset the timer timeout : out std_logic -- signal goes high on timeout ); end watchdog_timer; architecture Behavioral of watchdog_timer is constant TIMEOUT_LIMIT : integer := 1000000; -- example count limit signal counter : integer := 0; begin process(clk, reset_n) begin if reset_n = '0' then counter <= 0; timeout <= '0'; elsif rising_edge(clk) then if kick = '1' then counter <= 0; -- reset counter when kicked timeout <= '0'; else if counter < TIMEOUT_LIMIT then counter <= counter + 1; timeout <= '0'; else timeout <= '1'; -- timeout reached end if; end if; end if; end process; end Behavioral;
The kick input resets the timer counter to prevent timeout.
The timeout output signals when the timer reaches the limit without being reset.
kick signal high.kick <= '1'; -- reset the watchdog timer counterif timeout = '1' then -- perform system reset or error handling end if;
This program defines a simple watchdog timer with a small timeout limit for demonstration. The testbench resets the system, kicks the watchdog once, then stops kicking to let the timeout signal go high.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity watchdog_timer is port( clk : in std_logic; reset_n : in std_logic; kick : in std_logic; timeout : out std_logic ); end watchdog_timer; architecture Behavioral of watchdog_timer is constant TIMEOUT_LIMIT : integer := 10; -- small limit for demo signal counter : integer := 0; begin process(clk, reset_n) begin if reset_n = '0' then counter <= 0; timeout <= '0'; elsif rising_edge(clk) then if kick = '1' then counter <= 0; timeout <= '0'; else if counter < TIMEOUT_LIMIT then counter <= counter + 1; timeout <= '0'; else timeout <= '1'; end if; end if; end if; end process; end Behavioral; -- Testbench to simulate watchdog timer library ieee; use ieee.std_logic_1164.all; entity tb_watchdog is end tb_watchdog; architecture test of tb_watchdog is signal clk : std_logic := '0'; signal reset_n : std_logic := '0'; signal kick : std_logic := '0'; signal timeout : std_logic; component watchdog_timer port( clk : in std_logic; reset_n : in std_logic; kick : in std_logic; timeout : out std_logic ); end component; begin uut: watchdog_timer port map(clk, reset_n, kick, timeout); clk_process : process begin while true loop clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end loop; end process; stim_proc: process begin reset_n <= '0'; wait for 25 ns; reset_n <= '1'; -- Kick the watchdog at first kick <= '1'; wait for 20 ns; kick <= '0'; -- Do not kick, let timeout happen wait for 250 ns; wait; end process; end test;
Make sure the kick signal is sent regularly to prevent unwanted resets.
The timeout limit depends on your system clock speed and how long you want to wait before resetting.
A watchdog timer helps detect system freezes by counting time without a reset signal.
Use a kick signal to reset the timer counter regularly.
When the timer reaches its limit, it signals a timeout to trigger a system reset or error handling.
watchdog timer in a VHDL design?process(clk)
begin
if rising_edge(clk) then
if kick = '1' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;counter when kick is '1'?process(clk)
begin
if rising_edge(clk) then
if kick = '1' then
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;timeout signal when the counter reaches 1000 without a kick. Which approach correctly implements this behavior?Pass the test and this pattern moves unknown strong while earning +1 Grip toward your certificate.