Watchdog timer design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Watchdog timer reset signal behavior

Given the following VHDL snippet for a watchdog timer process, what is the output of the signal reset_out after 5 clock cycles if kick is never asserted?

VHDL

process(clk, reset_n)
begin
  if reset_n = '0' then
    counter <= 0;
    reset_out <= '0';
  elsif rising_edge(clk) then
    if kick = '1' then
      counter <= 0;
      reset_out <= '0';
    else
      if counter < 4 then
        counter <= counter + 1;
        reset_out <= '0';
      else
        reset_out <= '1';
      end if;
    end if;
  end if;
end process;

A reset_out remains '0' for all 5 cycles

B reset_out becomes '1' at the 4th clock cycle

C reset_out becomes '1' at the 5th clock cycle

D reset_out toggles between '0' and '1' every cycle

💡 Hint

Think about when the counter reaches the limit and what happens to reset_out.

The counter increments each clock cycle when kick is '0' until it reaches 4. On the 5th cycle, counter = 4 which is not < 4, so reset_out <= '1'.

🧠 Conceptual

intermediate

Purpose of the kick signal in a watchdog timer

In a watchdog timer design, what is the main purpose of the kick (or refresh) signal?

A To reset the watchdog timer counter to prevent system reset

B To reset the entire system immediately

C To disable the watchdog timer permanently

D To increase the watchdog timer timeout period

💡 Hint

Think about how the system avoids unwanted resets.

The kick signal resets the watchdog timer counter, preventing the timer from reaching its timeout and resetting the system.

🔧 Debug

advanced

Identify the error in this watchdog timer VHDL code

What error will occur when compiling this VHDL watchdog timer process?

VHDL

process(clk, reset_n)
begin
  if reset_n = '0' then
    counter <= 0;
    reset_out <= '0';
  elsif rising_edge(clk) then
    if kick = '1' then
      counter <= 0;
      reset_out <= '0';
    else
      if counter <= 4 then
        counter <= counter + 1;
        reset_out <= '0';
      else
        reset_out <= '1';
      end if;
    end if;
  end if;
end process;

A Runtime error: counter can overflow without limit

B No error, code compiles and runs correctly

C Logic error: reset_out never becomes '1'

D Syntax error: missing semicolon after counter increment

💡 Hint

Check the condition controlling the counter increment and possible overflow.

The code compiles without syntax errors. However, there is a logic issue: using <= 4 allows counter to increment from 4 to 5 before reset_out goes '1', delaying the timeout by one cycle. Additionally, counter is not assigned in the 'else' branch, which may infer a latch in synthesis.

📝 Syntax

advanced

Correct syntax for asynchronous reset in watchdog timer process

Which option shows the correct syntax for an asynchronous active-low reset in a VHDL watchdog timer process?

A

process(clk)
begin
  if rising_edge(clk) then
    if reset_n = '0' then
      counter <= 0;
    end if;
  end if;
end process;

B

process(reset_n)
begin
  if reset_n = '0' then
    counter <= 0;
  end if;
end process;

C

process(clk, reset_n)
begin
  if rising_edge(clk) then
    if reset_n = '0' then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

D

process(clk, reset_n)
begin
  if reset_n = '0' then
    counter <= 0;
  elsif rising_edge(clk) then
    counter <= counter + 1;
  end if;
end process;

💡 Hint

Asynchronous reset must be checked outside the clock edge condition.

Option D correctly checks reset_n asynchronously before the rising edge of clk.

🚀 Application

expert

Calculate watchdog timer timeout period

A watchdog timer uses a 16-bit counter clocked at 1 MHz. The timer resets the system when the counter reaches its maximum value. What is the approximate timeout period in seconds before reset occurs?

A Approximately 0.065 seconds

B Approximately 655 seconds

C Approximately 65.5 seconds

D Approximately 1.6 seconds

💡 Hint

Calculate the max count value and divide by clock frequency.

A 16-bit counter counts from 0 to 65535 (2^16 = 65536 cycles to reach max and trigger). At 1 MHz (1,000,000 Hz), timeout = 65536 / 1,000,000 ≈ 0.0655 seconds.

Practice

1. What is the main purpose of a watchdog timer in a VHDL design?

easy

A. To generate random numbers for encryption

B. To increase the clock speed of the system

C. To store data temporarily during processing

D. To detect system failures and trigger a reset if the system stops responding

Solution

1. Step 1: Understand the watchdog timer role

   A watchdog timer monitors system activity to detect failures.

2. Step 2: Identify the correct function

   It triggers a reset if the system stops responding to prevent lockup.

3. Final Answer:

   To detect system failures and trigger a reset if the system stops responding -> Option D

4. Quick Check:

   Watchdog timer = system failure detection [OK]

Hint: Watchdog timer resets system on failure detection [OK]

Common Mistakes:

• Confusing watchdog timer with clock generator
• Thinking it stores data
• Assuming it generates random numbers

2. Which of the following is the correct VHDL signal declaration for a 16-bit counter used in a watchdog timer?

easy

A. signal counter : std_logic_vector(15 downto 0);

B. signal counter : integer range 0 to 15;

C. signal counter : std_logic_vector(0 to 15);

D. signal counter : bit_vector(16 downto 1);

Solution

1. Step 1: Identify correct vector size and direction

   A 16-bit vector uses indices 15 downto 0 for standard logic vectors.

2. Step 2: Check each option

   signal counter : std_logic_vector(15 downto 0); uses std_logic_vector(15 downto 0), which is correct for 16 bits.

3. Final Answer:

   signal counter : std_logic_vector(15 downto 0); -> Option A

4. Quick Check:

   16-bit vector = (15 downto 0) [OK]

Hint: Use downto for descending bit ranges in vectors [OK]

Common Mistakes:

• Using integer range 0 to 15 instead of vector
• Using ascending range (0 to 15) incorrectly
• Using bit_vector instead of std_logic_vector

3. Given this VHDL process snippet for a watchdog timer counter:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= (others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What happens to counter when kick is '1'?

medium

A. Counter resets to zero

B. Counter increments by one

C. Counter holds its current value

D. Counter resets to all ones

Solution

1. Step 1: Analyze the condition when kick = '1'

   The code sets counter to (others => '0'), which means all bits zero.

2. Step 2: Understand the effect on counter

   Counter resets to zero instead of incrementing.

3. Final Answer:

   Counter resets to zero -> Option A

4. Quick Check:

   kick '1' resets counter = zero [OK]

Hint: kick '1' means reset counter to zero [OK]

Common Mistakes:

• Assuming counter increments on kick
• Thinking counter holds value on kick
• Confusing reset value with all ones

4. Identify the error in this VHDL watchdog timer process:

process(clk)
begin
  if rising_edge(clk) then
    if kick = '1' then
      counter <= 0;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

medium

A. Using rising_edge(clk) incorrectly

B. Assigning integer 0 to a std_logic_vector signal

C. Missing reset condition for counter

D. No error, code is correct

Solution

1. Step 1: Check signal type and assignment

   Counter is usually std_logic_vector; assigning integer 0 directly is invalid.

2. Step 2: Identify correct assignment method

   Must assign (others => '0') or convert integer to vector properly.

3. Final Answer:

   Assigning integer 0 to a std_logic_vector signal -> Option B

4. Quick Check:

   std_logic_vector needs vector assignment, not integer [OK]

Hint: Assign vectors with (others=>'0'), not integer 0 [OK]

Common Mistakes:

• Assigning integer directly to vector
• Ignoring reset conditions
• Misusing clock edge detection

5. You want to design a watchdog timer in VHDL that triggers a timeout signal when the counter reaches 1000 without a kick. Which approach correctly implements this behavior?

hard

A. Increment counter only when kick = '1'; reset counter when timeout = '1'; set timeout when counter > 1000

B. Reset counter on timeout; increment counter only when kick = '1'; set timeout when counter = 1000

C. Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000

D. Set timeout to '1' every clock cycle; reset counter only when kick = '0'

Solution

1. Step 1: Understand watchdog timer logic

   Counter increments every clock cycle unless reset by kick signal.

2. Step 2: Identify correct timeout condition

   Timeout triggers when counter reaches 1000 without reset.

3. Step 3: Evaluate options

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 matches correct logic: increment, reset on kick, timeout at 1000.

4. Final Answer:

   Increment counter each clock cycle; reset to zero on kick; set timeout when counter = 1000 -> Option C

5. Quick Check:

   Watchdog counts up, resets on kick, timeout at limit [OK]

Hint: Count up, reset on kick, timeout at limit [OK]

Common Mistakes:

• Incrementing only on kick
• Setting timeout every cycle
• Resetting counter incorrectly