Avoiding common synthesis pitfalls in VHDL

Introduction

When writing VHDL code for hardware, some mistakes can cause the design to not work as expected after synthesis. Avoiding these pitfalls helps your design behave correctly on real hardware.

When designing digital circuits to be implemented on FPGAs or ASICs

When writing VHDL code that will be converted into hardware gates

When you want your simulation results to match the actual hardware behavior

When optimizing your design for better performance and resource use

When debugging unexpected hardware behavior after synthesis

Syntax

VHDL

-- No specific syntax, but follow these rules:
-- 1. Avoid latches by ensuring all signals are assigned in all branches.
-- 2. Use synchronous resets instead of asynchronous when possible.
-- 3. Avoid combinational loops.
-- 4. Use proper clocked processes for sequential logic.
-- 5. Avoid inferred tri-state signals inside FPGA logic.

These are guidelines rather than strict syntax rules.

Following these helps synthesis tools generate correct hardware.

Examples

Proper synchronous reset avoids asynchronous reset pitfalls.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

This code can infer a latch because y is not assigned in all cases.

VHDL

process(a, b)
begin
  if a = '1' then
    y <= '1';
  elsif b = '1' then
    y <= '0';
  end if;
end process;

Assigning y in all branches avoids latch inference.

VHDL

process(a, b)
begin
  if a = '1' then
    y <= '1';
  else
    y <= '0';
  end if;
end process;

Sample Program

This example shows a safe synchronous counter with reset. It avoids common pitfalls like asynchronous reset and incomplete assignments.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity safe_counter is
  port(
    clk   : in std_logic;
    reset : in std_logic;
    count : out std_logic_vector(3 downto 0)
  );
end safe_counter;

architecture rtl of safe_counter is
  signal cnt : std_logic_vector(3 downto 0) := (others => '0');
begin
  process(clk)
  begin
    if rising_edge(clk) then
      if reset = '1' then
        cnt <= (others => '0');
      else
        cnt <= cnt + 1;
      end if;
    end if;
  end process;

  count <= cnt;
end rtl;

Important Notes

Always assign signals in every possible branch inside combinational processes to avoid latches.

Use synchronous resets to keep timing predictable.

Check for combinational loops which can cause synthesis errors or unstable hardware.

Summary

Avoid incomplete assignments to prevent unintended latches.

Prefer synchronous resets over asynchronous resets.

Write clear clocked processes for sequential logic.

Practice

1. Which practice helps avoid unintended latches in VHDL synthesis?

easy

A. Write combinational logic inside clocked processes

B. Use asynchronous resets only

C. Avoid using clock signals in processes

D. Assign all signals in every branch of a conditional statement

Solution

1. Step 1: Understand latch inference

   Unintended latches occur if signals are not assigned in all branches of a conditional, causing synthesis tools to infer memory elements.

2. Step 2: Assign signals in all branches

   By assigning signals in every branch, you ensure the signal always has a defined value, preventing latch inference.

3. Final Answer:

   Assign all signals in every branch of a conditional statement -> Option D

4. Quick Check:

   Complete signal assignment = no unintended latches [OK]

Hint: Always assign signals in all if-else branches to avoid latches [OK]

Common Mistakes:

• Leaving signals unassigned in some branches
• Using asynchronous resets incorrectly
• Mixing combinational and sequential logic improperly

2. Which of the following is the correct syntax for a synchronous process with a reset in VHDL?

easy

A. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

C. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

D. process(reset) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

Solution

1. Step 1: Check sensitivity list

   For synchronous reset, process sensitivity list includes only clock.

2. Step 2: Use nested if structure

   Clock edge first, then check reset inside for synchronous behavior.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; -> Option B

4. Quick Check:

   Reset inside clock edge = correct synchronous reset syntax [OK]

Hint: Sensitivity list only clk; nest reset inside rising_edge(clk) for synchronous reset [OK]

Common Mistakes:

• Including reset in sensitivity list (makes it asynchronous)
• Checking reset outside clock edge
• Using elsif instead of nested if

3. Given the following VHDL process, what will be the value of q after the rising edge of clk if reset is '0' and d is '1'?

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Previous value of q

Solution

1. Step 1: Check reset condition

   Reset is '0', so the reset branch is skipped.

2. Step 2: Check clock edge and assignment

   On rising edge of clk, q is assigned the value of d, which is '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Reset '0' + rising clk = q = d = '1' [OK]

Hint: If reset is '0', q follows d on clock edge [OK]

Common Mistakes:

• Confusing reset active level
• Assuming q keeps old value without clock edge
• Ignoring sensitivity list effects

4. Identify the synthesis issue in the following VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    end if;
end process;

medium

A. No issue; code is synthesizable as is

B. Syntax error due to missing sensitivity list signals

C. Unintended latch inferred because q is not assigned when enable = '0'

D. Process will not trigger on clock rising edge

Solution

1. Step 1: Analyze clocked process behavior

   In clocked processes, missing assignment in a branch implies hold previous value.

2. Step 2: Recognize standard template

   This is synthesizable as a flip-flop with enable; no latch inferred.

3. Final Answer:

   No issue; code is synthesizable as is -> Option A

4. Quick Check:

   Clocked process incomplete if = enabled FF hold [OK]

Hint: Incomplete assignments in clocked processes synthesize to enabled flip-flops [OK]

Common Mistakes:

• Confusing with combinational processes (which infer latches)
• Rewriting standard enabled FF template
• Mistaking intended hold for unintended latch

5. You want to design a synchronous counter with an active-high synchronous reset in VHDL. Which approach best avoids common synthesis pitfalls?

hard

A. Use a process with clock in sensitivity list; assign counter in all branches including reset and else

B. Use asynchronous reset only and assign counter only on clock rising edge

C. Assign counter only when reset is '0' and ignore other cases

D. Use combinational process without clock for counter increment

Solution

1. Step 1: Include only clock in sensitivity list

   For synchronous reset, only clock signal in process sensitivity list.

2. Step 2: Assign counter in all branches

   Assign counter to 0 on reset='1' and increment in else, all inside rising_edge(clk).

3. Final Answer:

   Use a process with clock in sensitivity list; assign counter in all branches including reset and else -> Option A

4. Quick Check:

   Synchronous reset + full assignments = safe synthesis [OK]

Hint: Always assign signals in all branches with clock in sensitivity list [OK]

Common Mistakes:

• Using asynchronous reset when synchronous is needed
• Missing assignments causing latches
• Using combinational logic for sequential counters