Dual-port RAM design in VHDL

Introduction

Dual-port RAM lets you read and write data at the same time using two separate ports. This helps make your digital circuits faster and more efficient.

When you want to read data from memory while writing new data at the same time.

In video processing where one part writes pixels and another reads them simultaneously.

For communication systems where data is received and sent at the same time.

In CPU designs where instructions and data are accessed concurrently.

When you need fast access to shared memory without waiting.

Syntax

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dual_port_ram is
  generic (
    DATA_WIDTH : integer := 8;
    ADDR_WIDTH : integer := 4
  );
  port (
    clk    : in  std_logic;
    we_a   : in  std_logic;
    addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    din_a  : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    dout_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
    we_b   : in  std_logic;
    addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
    din_b  : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    dout_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
  );
end dual_port_ram;

architecture rtl of dual_port_ram is
  type ram_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
  signal ram : ram_type := (others => (others => '0'));
begin
  process(clk) is
  begin
    if rising_edge(clk) then
      if we_a = '1' then
        ram(to_integer(unsigned(addr_a))) <= din_a;
      end if;
      dout_a <= ram(to_integer(unsigned(addr_a)));

      if we_b = '1' then
        ram(to_integer(unsigned(addr_b))) <= din_b;
      end if;
      dout_b <= ram(to_integer(unsigned(addr_b)));
    end if;
  end process;
end rtl;

This design uses a clocked process to handle both ports on the rising edge.

Each port has its own write enable, address, data input, and data output signals.

Examples

This example writes data to port A and reads the same address from port B.

VHDL

we_a <= '1';
addr_a <= "0001";
din_a <= "10101010";  -- Write data 0xAA to address 1

we_b <= '0';
addr_b <= "0001";      -- Read from address 1
-- dout_b will output "10101010" after clock

This example reads from port A and writes to port B at the same address.

VHDL

we_a <= '0';
addr_a <= "0010";      -- Read from address 2

we_b <= '1';
addr_b <= "0010";
din_b <= "11110000";  -- Write data 0xF0 to address 2

Sample Program

This test program writes data to the RAM using port A and port B, then reads it back from the other port to show simultaneous access.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_dual_port_ram is
end test_dual_port_ram;

architecture behavior of test_dual_port_ram is
  constant DATA_WIDTH : integer := 8;
  constant ADDR_WIDTH : integer := 4;

  signal clk    : std_logic := '0';
  signal we_a   : std_logic := '0';
  signal addr_a : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
  signal din_a  : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
  signal dout_a : std_logic_vector(DATA_WIDTH-1 downto 0);

  signal we_b   : std_logic := '0';
  signal addr_b : std_logic_vector(ADDR_WIDTH-1 downto 0) := (others => '0');
  signal din_b  : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
  signal dout_b : std_logic_vector(DATA_WIDTH-1 downto 0);

  component dual_port_ram is
    generic (
      DATA_WIDTH : integer := 8;
      ADDR_WIDTH : integer := 4
    );
    port (
      clk    : in  std_logic;
      we_a   : in  std_logic;
      addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
      din_a  : in  std_logic_vector(DATA_WIDTH-1 downto 0);
      dout_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
      we_b   : in  std_logic;
      addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
      din_b  : in  std_logic_vector(DATA_WIDTH-1 downto 0);
      dout_b : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
  end component;

begin
  uut: dual_port_ram
    generic map(DATA_WIDTH => DATA_WIDTH, ADDR_WIDTH => ADDR_WIDTH)
    port map(clk => clk, we_a => we_a, addr_a => addr_a, din_a => din_a, dout_a => dout_a,
             we_b => we_b, addr_b => addr_b, din_b => din_b, dout_b => dout_b);

  clk_process : process
  begin
    while true loop
      clk <= '0';
      wait for 5 ns;
      clk <= '1';
      wait for 5 ns;
    end loop;
  end process;

  stim_proc : process
  begin
    -- Write 0xAA to address 1 on port A
    we_a <= '1';
    addr_a <= "0001";
    din_a <= "10101010";

    -- Read from address 1 on port B
    we_b <= '0';
    addr_b <= "0001";
    wait for 10 ns;

    -- Write 0xF0 to address 2 on port B
    we_b <= '1';
    addr_b <= "0010";
    din_b <= "11110000";

    -- Read from address 2 on port A
    we_a <= '0';
    addr_a <= "0010";
    wait for 10 ns;

    -- Stop simulation
    wait;
  end process;
end behavior;

Important Notes

Both ports share the same memory array, so writing on one port updates the data seen by the other.

Reading and writing happen on the clock's rising edge, so outputs update after the clock cycle.

Be careful with simultaneous writes to the same address from both ports; behavior depends on your design.

Summary

Dual-port RAM allows two independent accesses at the same time.

Each port has its own control signals for reading and writing.

This design improves speed and flexibility in digital circuits.

Practice

1. What is the main advantage of using a dual-port RAM in VHDL designs?

easy

A. It simplifies the VHDL code by using only one port.

B. It doubles the memory size automatically.

C. It reduces the clock frequency needed.

D. It allows two independent memory accesses at the same time.

Solution

1. Step 1: Understand dual-port RAM functionality

   Dual-port RAM allows two separate accesses (read or write) simultaneously on different ports.

2. Step 2: Compare options with this feature

   Only 'It allows two independent memory accesses at the same time.' correctly states this advantage; others describe unrelated features.

3. Final Answer:

   It allows two independent memory accesses at the same time. -> Option D

4. Quick Check:

   Dual-port RAM = Two independent accesses [OK]

Hint: Dual-port RAM means two ports can access memory simultaneously [OK]

Common Mistakes:

• Thinking it doubles memory size automatically
• Assuming it reduces clock frequency
• Believing it simplifies code by using one port

2. Which of the following is the correct VHDL port declaration snippet for a dual-port RAM with separate read and write addresses?

easy

A. port(clk : in std_logic; addr : in std_logic_vector(3 downto 0); data : inout std_logic_vector(7 downto 0));

B. port(clk : in std_logic; addr_a : in std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : in std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0));

C. port(clk : in std_logic; addr_a : in std_logic_vector(7 downto 0); data_a : in std_logic_vector(3 downto 0); addr_b : in std_logic_vector(7 downto 0); data_b : in std_logic_vector(3 downto 0));

D. port(clk : in std_logic; addr_a : out std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : out std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0));

Solution

1. Step 1: Identify correct port directions and sizes

   Address ports are inputs, data ports are inout for read/write, clock is input.

2. Step 2: Match with options

   port(clk : in std_logic; addr_a : in std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : in std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0)); correctly declares two address inputs and two data inout ports with proper sizes and directions.

3. Final Answer:

   Port declaration with clk input, separate addr inputs, and data inout ports. -> Option B

4. Quick Check:

   Correct port directions and separate addresses = port(clk : in std_logic; addr_a : in std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : in std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0)); [OK]

Hint: Addresses are inputs, data ports are inout for dual-port RAM [OK]

Common Mistakes:

• Using addr ports as outputs
• Swapping data and address widths
• Missing separate ports for each RAM port

3. Given this VHDL process snippet for a dual-port RAM, what will be the output on data_b after the rising clock edge if we_a = '1' and addr_a = "0010" with data_a = "10101010"?

process(clk)
begin
  if rising_edge(clk) then
    if we_a = '1' then
      ram(to_integer(unsigned(addr_a))) <= data_a;
    end if;
    data_b <= ram(to_integer(unsigned(addr_b)));
  end if;
end process;

medium

A. Previous data at addr_b only, write does not affect read immediately

B. "10101010" regardless of addr_b

C. "10101010" if addr_b = "0010"; else previous data at addr_b

D. Undefined behavior due to simultaneous read/write

Solution

1. Step 1: Understand signal assignment timing in VHDL processes

   In a clocked process using signals, reads (<=) reflect current values before scheduled updates from this process.

2. Step 2: Trace the execution

   The write schedules ram(addr_a) <= data_a, but data_b <= ram(addr_b) reads the pre-update ram value, so always previous data at addr_b.

3. Final Answer:

   Previous data at addr_b only, write does not affect read immediately -> Option A

4. Quick Check:

   Signal RAM read sees old data before write update [OK]

Hint: VHDL signal RAM: read/write same cycle, read gets old data [OK]

Common Mistakes:

• Thinking write updates immediately for subsequent read in process
• Believing same-address read gets new data
• Assuming undefined behavior for read/write

4. Identify the error in this dual-port RAM VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    if we_a = '1' then
      ram(to_integer(unsigned(addr_a))) <= data_a;
    end if;
    if we_b = '1' then
      ram(to_integer(unsigned(addr_b))) <= data_b;
    end if;
    data_a <= ram(to_integer(unsigned(addr_a)));
    data_b <= ram(to_integer(unsigned(addr_b)));
  end if;
end process;

medium

A. Data ports should be declared as inputs, not outputs.

B. The clock signal is not used correctly in the process sensitivity list.

C. Simultaneous writes to the same RAM without conflict resolution can cause data corruption.

D. The process is missing a reset condition.

Solution

1. Step 1: Analyze simultaneous write conditions

   Both ports can write to RAM at the same clock edge; if addr_a = addr_b, writes conflict without arbitration.

2. Step 2: Check other options

   Clock is correctly used; data ports can be inout; reset is optional but not error here.

3. Final Answer:

   Simultaneous writes to the same RAM without conflict resolution can cause data corruption. -> Option C

4. Quick Check:

   Dual-port RAM needs write conflict handling [OK]

Hint: Check if both ports write same address simultaneously [OK]

Common Mistakes:

• Ignoring write conflicts on same address
• Thinking clock usage is incorrect
• Assuming reset is mandatory for all RAM

5. You need to design a dual-port RAM in VHDL where Port A is write-only and Port B is read-only. Which approach correctly implements this behavior?

hard

A. Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock.

B. Use a single data port for both read and write and control direction with a signal inside the process.

C. Declare both ports as inout and use tri-state buffers to control read/write direction.

D. Use two separate RAM blocks, one for write and one for read, connected externally.

Solution

1. Step 1: Understand port direction requirements

   Port A is write-only, so data port must be input; Port B is read-only, so data port must be output.

2. Step 2: Choose correct implementation

   Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock. matches these requirements with separate addresses and synchronized clock, suitable for dual-port RAM.

3. Final Answer:

   Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock. -> Option A

4. Quick Check:

   Write-only input and read-only output ports = Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock. [OK]

Hint: Match port directions to read/write roles explicitly [OK]

Common Mistakes:

• Using inout ports unnecessarily
• Trying to control direction inside process
• Splitting RAM into two blocks unnecessarily