UART transmitter and receiver in VHDL - Step-by-Step Execution

Concept Flow - UART transmitter and receiver

Start Bit Detect

↓

Shift Out Data Bits

↓

Send Stop Bit

↓

Idle State

↓

Receive Start Bit

↓

Shift In Data Bits

↓

Check Stop Bit

↓

Data Ready

↓

Idle State

The UART transmitter sends data bits one by one framed by start and stop bits. The receiver waits for a start bit, then reads data bits, checks the stop bit, and signals data ready.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if tx_start = '1' then
      tx_shift_reg <= '0' & data_in & '1';
      tx_busy <= '1';
    end if;
  end if;
end process;

This code starts UART transmission by loading data with start (0) and stop (1) bits into a shift register and sets busy flag.

Execution Table

Step	Signal/Variable	Value	Action	Description
1	tx_start	'1'	Load shift register	Load data_in with start and stop bits into tx_shift_reg
2	tx_shift_reg	'0' & data_in & '1'	Start shifting	Shift register ready to send bits serially
3	tx_busy	'1'	Set busy	Indicates transmission in progress
4	tx_out	'0'	Send start bit	Transmit start bit (logic 0) first
5	tx_out	data_in(0)	Send data bit 0	Transmit first data bit
6	tx_out	data_in(1)	Send data bit 1	Transmit second data bit
7	tx_out	...	Send remaining data bits	Transmit all data bits one by one
8	tx_out	'1'	Send stop bit	Transmit stop bit (logic 1) to end frame
9	tx_busy	'0'	Clear busy	Transmission complete
10	rx_in	'0'	Detect start bit	Receiver detects start bit to begin reception
11	rx_shift_reg	shift in bits	Shift in data bits	Receiver shifts in each data bit serially
12	rx_stop_bit	'1'	Check stop bit	Receiver checks stop bit correctness
13	data_ready	'1'	Set data ready	Receiver signals data is ready to read
14	Idle	-	Wait for next frame	Both transmitter and receiver idle until next start bit

💡 Transmission ends after stop bit sent; reception ends after stop bit checked and data ready set.

Variable Tracker

Variable	Start	After Step 1	After Step 4	After Step 8	After Step 9	After Step 13
tx_shift_reg	undefined	'0' & data_in & '1'	shifting bits	empty	empty	empty
tx_busy	'0'	'1'	'1'	'1'	'0'	'0'
tx_out	idle ('1')	'0'	data bits	'1'	'1'	'1'
rx_shift_reg	empty	empty	empty	shifting bits	shifting bits	full data
data_ready	'0'	'0'	'0'	'0'	'0'	'1'

Key Moments - 3 Insights

Why do we add a '0' at the start and a '1' at the end of the data in tx_shift_reg?

The '0' is the start bit signaling the beginning of transmission, and the '1' is the stop bit signaling the end. This framing is essential for the receiver to know when data starts and ends, as shown in execution_table steps 1, 4, and 8.

How does the receiver know when to start reading data bits?

The receiver waits for the start bit (logic 0) on rx_in, which triggers shifting in data bits. This is shown in execution_table step 10 where rx_in detects '0' to start reception.

What does tx_busy signal indicate during transmission?

tx_busy is set to '1' when transmission starts (step 3) and cleared to '0' after the stop bit is sent (step 9). It tells other parts of the system that the transmitter is busy sending data.

Visual Quiz - 3 Questions

Look at the execution_table, what value does tx_out have at step 4?

A '1' (stop bit)

B '0' (start bit)

C data_in(0)

D idle ('1')

💡 Hint

Refer to execution_table row with Step 4 showing tx_out sends the start bit '0'.

At which step does the receiver signal that data is ready?

A Step 13

B Step 10

C Step 8

D Step 4

💡 Hint

Check execution_table row 13 where data_ready is set to '1'.

If tx_busy was never cleared to '0', what would happen?

A Transmission would stop normally

B Receiver would never detect start bit

C Transmitter would keep sending data endlessly

D Data_ready would never be set

💡 Hint

Look at variable_tracker for tx_busy staying '1' after step 9 means transmitter stays busy.

Concept Snapshot

UART Transmitter and Receiver in VHDL:
- Transmitter frames data with start (0) and stop (1) bits.
- Data sent bit-by-bit via shift register.
- Receiver waits for start bit, shifts in data bits, checks stop bit.
- tx_busy signals transmission in progress.
- data_ready signals reception complete.

Full Transcript

This visual execution trace shows how a UART transmitter and receiver work in VHDL. The transmitter starts by loading data with start and stop bits into a shift register and sets a busy flag. It sends the start bit first, then data bits one by one, and finally the stop bit. The busy flag clears after transmission ends. The receiver detects the start bit on its input, shifts in data bits, checks the stop bit, and then signals that data is ready. Variables like tx_shift_reg, tx_busy, tx_out, rx_shift_reg, and data_ready change values step-by-step as shown in the tables. Key moments clarify why start/stop bits are needed, how the receiver knows when to start reading, and the role of the busy signal. The quiz questions help reinforce understanding by referencing specific steps and variable values. This trace helps beginners see exactly how UART communication happens inside hardware described by VHDL.

Practice

1. What is the main role of the UART transmitter in a communication system?

easy

A. To send data bits serially with start and stop bits

B. To receive data bits and convert them to parallel form

C. To amplify the signal strength for transmission

D. To encrypt data before sending

Solution

1. Step 1: Understand UART transmitter function

   The UART transmitter converts parallel data into serial form and adds start and stop bits for synchronization.

2. Step 2: Differentiate transmitter from receiver roles

   The receiver listens and converts serial data back to parallel, so amplification or encryption is not the transmitter's main role.

3. Final Answer:

   To send data bits serially with start and stop bits -> Option A

4. Quick Check:

   Transmitter sends serial data = A [OK]

Hint: Remember: transmitter sends serial bits with start/stop [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking transmitter encrypts data
• Assuming transmitter amplifies signals

2. Which of the following is the correct VHDL port declaration for a UART receiver input line named rx?

easy

A. rx : out std_logic;

B. rx : inout std_logic_vector(7 downto 0);

C. rx : in std_logic;

D. rx : buffer std_logic_vector(7 downto 0);

Solution

1. Step 1: Identify direction of UART receiver input

   The receiver reads data from the input line, so the port direction must be 'in'.

2. Step 2: Check data type for single UART line

   UART input is a single bit line, so type is std_logic, not a vector.

3. Final Answer:

   rx : in std_logic; -> Option C

4. Quick Check:

   Receiver input is 'in std_logic' = C [OK]

Hint: Input lines use 'in std_logic' for single UART signals [OK]

Common Mistakes:

• Using 'out' instead of 'in' for receiver input
• Using std_logic_vector for single bit line
• Using 'buffer' or 'inout' incorrectly

3. Given this VHDL snippet for a UART transmitter process, what is the value of tx_line after sending the start bit?

process(clk)
begin
  if rising_edge(clk) then
    if state = IDLE then
      tx_line <= '1';
    elsif state = START_BIT then
      tx_line <= '0';
    end if;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. 'X'

Solution

1. Step 1: Analyze process behavior at START_BIT state

   When state equals START_BIT, the code sets tx_line to '0', representing the start bit.

2. Step 2: Confirm output value after start bit

   Since the start bit is '0', tx_line will be '0' during START_BIT state.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Start bit = '0' on tx_line = B [OK]

Hint: Start bit in UART is always '0' on tx_line [OK]

Common Mistakes:

• Confusing start bit with idle line '1'
• Assuming 'Z' or 'X' values appear
• Ignoring state conditions

4. Identify the error in this UART receiver process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if rx = '0' then
      data <= rx_data & rx;
    end if;
  end if;
end process;

medium

A. Missing reset condition for data register

B. Concatenation order is incorrect for data assembly

C. rx signal should be '1' to detect start bit

D. Process sensitivity list is incomplete

Solution

1. Step 1: Check process for reset handling

   The process lacks a reset condition to clear or initialize 'data', which is essential for reliable UART reception.

2. Step 2: Validate other parts

   Concatenation order and rx = '0' for start bit detection are correct; sensitivity list with clk is standard.

3. Final Answer:

   Missing reset condition for data register -> Option A

4. Quick Check:

   Reset needed to clear data = A [OK]

Hint: Always include reset in UART receiver process [OK]

Common Mistakes:

• Ignoring reset causes data corruption
• Thinking start bit is '1'
• Misunderstanding concatenation order

5. You want to design a UART transmitter in VHDL that sends 8-bit data with 1 start bit, 1 stop bit, and no parity. Which sequence correctly represents the bits sent on the tx line for data byte "10110011"?

hard

A. Start bit '0', data bits MSB first '10110011', stop bit '1'

B. Start bit '1', data bits MSB first '10110011', stop bit '0'

C. Start bit '0', data bits LSB first '11001101', stop bit '0'

D. Start bit '0', data bits LSB first '11001101', stop bit '1'

Solution

1. Step 1: Recall UART bit order and framing

   UART sends a start bit '0', then data bits least significant bit (LSB) first, then stop bit '1'.

2. Step 2: Convert data byte to LSB first sequence

   Data '10110011' MSB to LSB is bits 7 to 0. LSB first means sending '11001101'.

3. Step 3: Confirm start and stop bits

   Start bit is '0', stop bit is '1' as per UART standard.

4. Final Answer:

   Start bit '0', data bits LSB first '11001101', stop bit '1' -> Option D

5. Quick Check:

   UART sends start '0', LSB first, stop '1' = D [OK]

Hint: UART sends LSB first with start '0' and stop '1' bits [OK]

Common Mistakes:

• Sending MSB first instead of LSB first
• Using wrong stop bit value
• Confusing start bit as '1'