UART transmitter and receiver in VHDL - Mini Project: Build & Apply

UART transmitter and receiver

📖 Scenario: You are designing a simple UART (Universal Asynchronous Receiver/Transmitter) system to send and receive data serially between two devices. UART is commonly used in embedded systems to communicate over serial ports.In this project, you will create a VHDL design for a UART transmitter and receiver. The transmitter will convert parallel data into serial bits, and the receiver will convert serial bits back into parallel data.

🎯 Goal: Build a UART transmitter and receiver in VHDL that can send and receive 8-bit data with start and stop bits at a fixed baud rate.

📋 What You'll Learn

Create a data signal to hold 8-bit data to transmit

Create a baud rate generator signal for timing

Implement UART transmitter logic to send start bit, data bits, and stop bit serially

Implement UART receiver logic to detect start bit, sample data bits, and stop bit

Output the received 8-bit data

Print the received data in simulation

💡 Why This Matters

🌍 Real World

UART communication is widely used in embedded systems, microcontrollers, and serial devices to send data over short distances using simple wiring.

💼 Career

Understanding UART design in VHDL is important for FPGA and hardware engineers working on communication interfaces and embedded system designs.

1

DATA SETUP: Define the 8-bit data signal to transmit

Create a signal called tx_data of type std_logic_vector(7 downto 0) and set it to "10101010".

VHDL

-- Your code here
-- Create signal tx_data with value "10101010"

Hint

Use signal tx_data : std_logic_vector(7 downto 0) := "10101010"; to create the data signal.

2

CONFIGURATION: Create a baud rate clock enable signal

Create a signal called baud_tick of type std_logic and initialize it to '0'. This signal will be used to time the UART bits.

VHDL

signal tx_data : std_logic_vector(7 downto 0) := "10101010";
-- Your code here
-- Create signal baud_tick initialized to '0'

Hint

Use signal baud_tick : std_logic := '0'; to create the baud rate tick signal.

3

CORE LOGIC: Implement UART transmitter process

Write a process called uart_tx_process that triggers on the rising edge of a clock signal clk. Inside, use a variable bit_index to send the start bit ('0'), then each bit of tx_data from LSB to MSB, and finally the stop bit ('1') on an output signal tx_serial. Use baud_tick = '1' to move to the next bit.

VHDL

signal tx_data : std_logic_vector(7 downto 0) := "10101010";
signal baud_tick : std_logic := '0';
-- Your code here
-- Implement uart_tx_process with clk and baud_tick to output tx_serial

Hint

Use a process triggered by clk and check baud_tick = '1' to send bits in order: start bit, data bits, stop bit.

4

OUTPUT: Print received data after UART reception

Assuming you have a signal rx_data of type std_logic_vector(7 downto 0) holding received data, write a process triggered on clk that prints the received data as a binary string using report statement when a signal data_ready is '1'.

VHDL

signal tx_data : std_logic_vector(7 downto 0) := "10101010";
signal baud_tick : std_logic := '0';
signal tx_serial : std_logic := '1';
signal rx_data : std_logic_vector(7 downto 0);
signal data_ready : std_logic := '0';

process(clk)
    variable bit_index : integer range 0 to 9 := 0;
begin
    if rising_edge(clk) then
        if baud_tick = '1' then
            case bit_index is
                when 0 => tx_serial  tx_serial  tx_serial  null;
            end case;
            if bit_index = 9 then
                bit_index := 0;
            else
                bit_index := bit_index + 1;
            end if;
        end if;
    end if;
end process;

-- Your code here
-- Print rx_data when data_ready = '1'

Hint

Use a process triggered by clk and check data_ready = '1' to print rx_data using report.

Practice

1. What is the main role of the UART transmitter in a communication system?

easy

A. To send data bits serially with start and stop bits

B. To receive data bits and convert them to parallel form

C. To amplify the signal strength for transmission

D. To encrypt data before sending

Solution

1. Step 1: Understand UART transmitter function

   The UART transmitter converts parallel data into serial form and adds start and stop bits for synchronization.

2. Step 2: Differentiate transmitter from receiver roles

   The receiver listens and converts serial data back to parallel, so amplification or encryption is not the transmitter's main role.

3. Final Answer:

   To send data bits serially with start and stop bits -> Option A

4. Quick Check:

   Transmitter sends serial data = A [OK]

Hint: Remember: transmitter sends serial bits with start/stop [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking transmitter encrypts data
• Assuming transmitter amplifies signals

2. Which of the following is the correct VHDL port declaration for a UART receiver input line named rx?

easy

A. rx : out std_logic;

B. rx : inout std_logic_vector(7 downto 0);

C. rx : in std_logic;

D. rx : buffer std_logic_vector(7 downto 0);

Solution

1. Step 1: Identify direction of UART receiver input

   The receiver reads data from the input line, so the port direction must be 'in'.

2. Step 2: Check data type for single UART line

   UART input is a single bit line, so type is std_logic, not a vector.

3. Final Answer:

   rx : in std_logic; -> Option C

4. Quick Check:

   Receiver input is 'in std_logic' = C [OK]

Hint: Input lines use 'in std_logic' for single UART signals [OK]

Common Mistakes:

• Using 'out' instead of 'in' for receiver input
• Using std_logic_vector for single bit line
• Using 'buffer' or 'inout' incorrectly

3. Given this VHDL snippet for a UART transmitter process, what is the value of tx_line after sending the start bit?

process(clk)
begin
  if rising_edge(clk) then
    if state = IDLE then
      tx_line <= '1';
    elsif state = START_BIT then
      tx_line <= '0';
    end if;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. 'X'

Solution

1. Step 1: Analyze process behavior at START_BIT state

   When state equals START_BIT, the code sets tx_line to '0', representing the start bit.

2. Step 2: Confirm output value after start bit

   Since the start bit is '0', tx_line will be '0' during START_BIT state.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Start bit = '0' on tx_line = B [OK]

Hint: Start bit in UART is always '0' on tx_line [OK]

Common Mistakes:

• Confusing start bit with idle line '1'
• Assuming 'Z' or 'X' values appear
• Ignoring state conditions

4. Identify the error in this UART receiver process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if rx = '0' then
      data <= rx_data & rx;
    end if;
  end if;
end process;

medium

A. Missing reset condition for data register

B. Concatenation order is incorrect for data assembly

C. rx signal should be '1' to detect start bit

D. Process sensitivity list is incomplete

Solution

1. Step 1: Check process for reset handling

   The process lacks a reset condition to clear or initialize 'data', which is essential for reliable UART reception.

2. Step 2: Validate other parts

   Concatenation order and rx = '0' for start bit detection are correct; sensitivity list with clk is standard.

3. Final Answer:

   Missing reset condition for data register -> Option A

4. Quick Check:

   Reset needed to clear data = A [OK]

Hint: Always include reset in UART receiver process [OK]

Common Mistakes:

• Ignoring reset causes data corruption
• Thinking start bit is '1'
• Misunderstanding concatenation order

5. You want to design a UART transmitter in VHDL that sends 8-bit data with 1 start bit, 1 stop bit, and no parity. Which sequence correctly represents the bits sent on the tx line for data byte "10110011"?

hard

A. Start bit '0', data bits MSB first '10110011', stop bit '1'

B. Start bit '1', data bits MSB first '10110011', stop bit '0'

C. Start bit '0', data bits LSB first '11001101', stop bit '0'

D. Start bit '0', data bits LSB first '11001101', stop bit '1'

Solution

1. Step 1: Recall UART bit order and framing

   UART sends a start bit '0', then data bits least significant bit (LSB) first, then stop bit '1'.

2. Step 2: Convert data byte to LSB first sequence

   Data '10110011' MSB to LSB is bits 7 to 0. LSB first means sending '11001101'.

3. Step 3: Confirm start and stop bits

   Start bit is '0', stop bit is '1' as per UART standard.

4. Final Answer:

   Start bit '0', data bits LSB first '11001101', stop bit '1' -> Option D

5. Quick Check:

   UART sends start '0', LSB first, stop '1' = D [OK]

Hint: UART sends LSB first with start '0' and stop '1' bits [OK]

Common Mistakes:

• Sending MSB first instead of LSB first
• Using wrong stop bit value
• Confusing start bit as '1'