UART transmitter and receiver in VHDL - Deep Dive

Overview - UART transmitter and receiver

What is it?

UART stands for Universal Asynchronous Receiver/Transmitter. It is a hardware communication protocol that sends and receives data one bit at a time without a shared clock signal. The UART transmitter converts parallel data into serial form to send it, while the receiver converts the serial data back into parallel form. This allows devices to communicate over simple wires using start, data, parity, and stop bits.

Why it matters

UART enables simple and reliable communication between devices like microcontrollers, sensors, and computers without needing complex wiring or synchronization. Without UART, devices would struggle to exchange data efficiently over long distances or with minimal hardware. It is widely used in embedded systems, making many everyday electronics work smoothly.

Where it fits

Before learning UART, you should understand basic digital logic, binary data, and clock signals. After mastering UART transmitter and receiver design, you can explore other serial communication protocols like SPI or I2C, or advanced UART features like flow control and error detection.

Mental Model

Core Idea

UART transmitter and receiver work together to convert parallel data into timed serial bits and back, using start and stop signals to frame the data without a shared clock.

Think of it like...

Imagine sending a message by flashing a flashlight in a pattern: the transmitter flashes dots and dashes one by one, and the receiver watches and decodes the pattern back into words without needing a shared clock, just by knowing when the message starts and ends.

┌───────────────┐       ┌───────────────┐
│ Parallel Data │──────▶│ UART Transmit │
└───────────────┘       └───────┬───────┘
                                │ Serial bits with start/stop
                                ▼
                        ┌───────────────┐
                        │ UART Receive  │
                        └───────┬───────┘
                                │ Parallel Data out
                                ▼
                        ┌───────────────┐
                        │ Data Receiver │
                        └───────────────┘

Build-Up - 8 Steps

1

Foundation

Understanding UART Basics

Concept: Introduce UART communication principles and signal framing.

UART sends data serially using a start bit, data bits, optional parity bit, and stop bit(s). The start bit signals the beginning of data, data bits carry the actual information, parity helps detect errors, and stop bits mark the end. Data is sent least significant bit first, and the transmitter and receiver agree on baud rate (speed).

Result

You know the structure of UART frames and how data is organized for transmission.

Understanding the framing of UART data is essential because it allows asynchronous communication without a shared clock.

2

Foundation

Parallel to Serial Conversion

Concept: Learn how parallel data is converted into serial bits for transmission.

The UART transmitter takes an 8-bit parallel input and sends it out one bit at a time, starting with the start bit (logic 0), then data bits, optional parity, and stop bit(s) (logic 1). This requires a shift register and a baud rate clock to time each bit.

Result

You can explain how parallel data becomes a timed serial stream.

Knowing how parallel data is serialized helps you design the transmitter logic and timing control.

3

Intermediate

Serial to Parallel Conversion

Concept: Learn how the receiver converts serial bits back into parallel data.

The UART receiver watches the serial line for a start bit (logic 0). Once detected, it samples the incoming bits at the baud rate to capture data bits, parity, and stop bits. It then assembles these bits into parallel data for the system. This requires a state machine and timing logic to sample bits in the middle of their expected time slot.

Result

You understand how the receiver reconstructs data from serial bits.

Recognizing the importance of precise timing in sampling bits prevents data corruption.

4

Intermediate

Handling Baud Rate and Timing

🤔Before reading on: do you think the receiver needs to sample bits exactly at the start of each bit period or in the middle? Commit to your answer.

Concept: Explore how baud rate clocks synchronize transmitter and receiver without a shared clock.

Both transmitter and receiver use a baud rate clock derived from a common frequency source. The transmitter sends bits timed by this clock. The receiver detects the start bit and then samples each bit in the middle of its expected time slot to avoid errors caused by slight timing differences.

Result

You know how timing ensures reliable data transfer despite asynchronous clocks.

Understanding mid-bit sampling explains how UART tolerates small clock mismatches.

5

Intermediate

Error Detection with Parity Bit

🤔Before reading on: do you think parity bits can correct errors or only detect them? Commit to your answer.

Concept: Introduce parity bits as a simple error detection method in UART communication.

Parity bits add an extra bit to the data frame that makes the total number of 1s either even (even parity) or odd (odd parity). The receiver checks parity to detect if a single bit error occurred during transmission. Parity cannot fix errors, only signal that something went wrong.

Result

You understand how parity helps detect transmission errors.

Knowing parity's limits helps you decide when more robust error handling is needed.

6

Advanced

VHDL Implementation of UART Transmitter

🤔Before reading on: do you think a UART transmitter needs a complex state machine or simple counters? Commit to your answer.

Concept: Learn how to write VHDL code for a UART transmitter using shift registers and timing control.

The transmitter uses a shift register loaded with start bit, data bits, parity, and stop bits. A baud rate clock enables shifting out one bit per clock cycle. A state machine controls loading data and shifting bits. The output line changes according to the current bit in the shift register.

Result

You can write synthesizable VHDL code for a UART transmitter.

Understanding the hardware structure behind the code clarifies how timing and data flow are controlled.

7

Advanced

VHDL Implementation of UART Receiver

🤔Before reading on: do you think the receiver samples bits continuously or only after detecting a start bit? Commit to your answer.

Concept: Learn how to write VHDL code for a UART receiver with start bit detection and bit sampling.

The receiver waits for a falling edge indicating the start bit. It then uses a baud rate clock to sample bits in the middle of each bit period. A shift register collects bits, and a state machine manages the process. After receiving all bits, the data is output in parallel form.

Result

You can write synthesizable VHDL code for a UART receiver.

Knowing how to synchronize sampling after start bit detection is key to reliable reception.

8

Expert

Handling Clock Differences and Noise Robustness

🤔Before reading on: do you think UART can handle any clock difference or only small mismatches? Commit to your answer.

Concept: Explore how UART tolerates clock mismatches and noise, and what design choices improve robustness.

UART tolerates small clock differences by sampling bits in the middle of their period and using stop bits as buffers. Excessive clock drift or noise can cause framing errors. Designers add oversampling (sampling multiple times per bit) and majority voting to improve noise immunity. Proper line termination and shielding also help.

Result

You understand the limits of UART timing and how to design for real-world conditions.

Knowing UART's tolerance boundaries helps prevent communication failures in noisy or asynchronous environments.

Under the Hood

Internally, UART transmitter uses a shift register loaded with framed data bits and a baud rate clock to shift out bits serially. The receiver uses a state machine to detect the start bit, then samples incoming bits at precise intervals using a baud rate clock derived from a local oscillator. Both sides rely on timing logic to maintain synchronization without a shared clock, using start and stop bits as framing signals.

Why designed this way?

UART was designed for simplicity and minimal wiring, avoiding the need for a shared clock line. Using start and stop bits allows asynchronous communication, making UART flexible and easy to implement in hardware. Alternatives like synchronous serial require more complex clock sharing, which was costly and complicated in early hardware designs.

┌───────────────┐       ┌───────────────┐       ┌───────────────┐
│ Parallel Data │──────▶│ Shift Register│──────▶│ Serial Output │
└───────────────┘       └───────┬───────┘       └───────┬───────┘
                                │                       │
                        Baud Rate Clock           Serial Line
                                │                       │
                                ▼                       ▼
                        ┌───────────────┐       ┌───────────────┐
                        │ Start Bit     │◀──────│ Serial Input  │
                        │ Detection    │        └───────┬───────┘
                        └───────┬───────┘                │
                                │                  Baud Rate Clock
                        ┌───────▼───────┐                │
                        │ Shift Register│◀───────────────┘
                        └───────┬───────┘
                                │
                        ┌───────▼───────┐
                        │ Parallel Data │
                        └───────────────┘

Myth Busters - 4 Common Misconceptions

Quick: Does UART require a shared clock signal between devices? Commit to yes or no.

Common Belief: UART devices must share a clock signal to synchronize data transfer.

Reality: UART communication is asynchronous and does not require a shared clock; it uses start and stop bits to frame data and timing to sample bits.

Why it matters: Assuming a shared clock leads to wrong hardware designs and confusion about UART's asynchronous nature.

Quick: Can parity bits correct errors or only detect them? Commit to your answer.

Common Belief: Parity bits can fix errors in the transmitted data.

Reality: Parity bits only detect single-bit errors; they cannot correct errors.

Why it matters: Relying on parity for error correction can cause undetected data corruption and system failures.

Quick: Does UART guarantee error-free communication regardless of noise? Commit to yes or no.

Common Belief: UART communication is always error-free if baud rates match.

Reality: UART can suffer from errors due to noise, clock mismatches, or line issues; error detection and proper design are needed.

Why it matters: Ignoring error sources leads to unreliable communication and debugging challenges.

Quick: Does the UART receiver sample bits at the start or middle of each bit period? Commit to your answer.

Common Belief: The receiver samples bits right at the start of each bit period.

Reality: The receiver samples bits in the middle of each bit period to avoid timing errors.

Why it matters: Sampling at the wrong time causes bit errors and data corruption.

Expert Zone

1

UART receivers often use oversampling (e.g., 16x baud rate) to improve timing accuracy and noise immunity.

2

Stop bits not only mark frame end but also provide a recovery time for the receiver before the next frame.

3

In multi-drop UART networks, addressing and collision detection require additional protocols beyond basic UART.

When NOT to use

UART is not suitable for high-speed or multi-device bus communication where protocols like SPI, I2C, or CAN are better. For guaranteed error correction, use protocols with CRC or forward error correction instead of simple parity.

Production Patterns

In real systems, UART is used for debugging consoles, GPS modules, Bluetooth modules, and serial communication between microcontrollers. Designers often implement FIFO buffers, interrupt-driven I/O, and configurable baud rates for flexibility and performance.

Connections

SPI (Serial Peripheral Interface)

Both are serial communication protocols but SPI is synchronous while UART is asynchronous.

Understanding UART's asynchronous nature highlights the tradeoffs between wiring complexity and synchronization in serial protocols.

Human Speech Communication

Both use start and stop signals to frame meaningful data without a shared clock.

Knowing how humans use pauses and cues to understand speech helps grasp how UART frames data without a clock.

Morse Code Signaling

UART's serial bit transmission is similar to sending dots and dashes in Morse code over time.

Recognizing UART as timed signaling clarifies how data can be sent reliably one bit at a time.

Common Pitfalls

#1 Sampling bits at the wrong time causing data errors.

Wrong approach:

process(clk) begin
if rising_edge(clk) then
if rx_line = '0' then -- start bit detected
sample_bit <= rx_line;
end if;
end if;
end process;

Correct approach:

process(clk) begin
if rising_edge(clk) then
if start_bit_detected then
sample_bit <= sample_rx_line_at_mid_bit_time;
end if;
end if;
end process;

Root cause:

Misunderstanding that sampling should occur in the middle of the bit period, not immediately at start bit detection.

#2 Not including stop bits in transmitted frame causing framing errors.

Wrong approach:

shift_register <= start_bit & data_bits & parity_bit; -- no stop bit

Correct approach:

shift_register <= start_bit & data_bits & parity_bit & stop_bit;

Root cause:

Overlooking the importance of stop bits for framing and receiver synchronization.

#3 Assuming parity bit corrects errors leading to undetected data corruption.

Wrong approach:

if parity_check = false then
correct_error(); -- incorrect assumption
end if;

Correct approach:

if parity_check = false then
flag_error(); -- detect only
end if;

Root cause:

Confusing error detection with error correction capabilities of parity bits.

Key Takeaways

UART enables asynchronous serial communication by framing data with start and stop bits, eliminating the need for a shared clock.

The transmitter converts parallel data into a timed serial stream, while the receiver reconstructs parallel data by sampling bits in the middle of their time slots.

Parity bits provide simple error detection but cannot correct errors, so additional error handling may be necessary.

Precise timing and synchronization are critical for reliable UART communication, especially in noisy or clock-drift environments.

Understanding UART's design and limitations helps in choosing the right communication protocol and implementing robust hardware designs.

Practice

1. What is the main role of the UART transmitter in a communication system?

easy

A. To send data bits serially with start and stop bits

B. To receive data bits and convert them to parallel form

C. To amplify the signal strength for transmission

D. To encrypt data before sending

Solution

1. Step 1: Understand UART transmitter function

   The UART transmitter converts parallel data into serial form and adds start and stop bits for synchronization.

2. Step 2: Differentiate transmitter from receiver roles

   The receiver listens and converts serial data back to parallel, so amplification or encryption is not the transmitter's main role.

3. Final Answer:

   To send data bits serially with start and stop bits -> Option A

4. Quick Check:

   Transmitter sends serial data = A [OK]

Hint: Remember: transmitter sends serial bits with start/stop [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking transmitter encrypts data
• Assuming transmitter amplifies signals

2. Which of the following is the correct VHDL port declaration for a UART receiver input line named rx?

easy

A. rx : out std_logic;

B. rx : inout std_logic_vector(7 downto 0);

C. rx : in std_logic;

D. rx : buffer std_logic_vector(7 downto 0);

Solution

1. Step 1: Identify direction of UART receiver input

   The receiver reads data from the input line, so the port direction must be 'in'.

2. Step 2: Check data type for single UART line

   UART input is a single bit line, so type is std_logic, not a vector.

3. Final Answer:

   rx : in std_logic; -> Option C

4. Quick Check:

   Receiver input is 'in std_logic' = C [OK]

Hint: Input lines use 'in std_logic' for single UART signals [OK]

Common Mistakes:

• Using 'out' instead of 'in' for receiver input
• Using std_logic_vector for single bit line
• Using 'buffer' or 'inout' incorrectly

3. Given this VHDL snippet for a UART transmitter process, what is the value of tx_line after sending the start bit?

process(clk)
begin
  if rising_edge(clk) then
    if state = IDLE then
      tx_line <= '1';
    elsif state = START_BIT then
      tx_line <= '0';
    end if;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. 'X'

Solution

1. Step 1: Analyze process behavior at START_BIT state

   When state equals START_BIT, the code sets tx_line to '0', representing the start bit.

2. Step 2: Confirm output value after start bit

   Since the start bit is '0', tx_line will be '0' during START_BIT state.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Start bit = '0' on tx_line = B [OK]

Hint: Start bit in UART is always '0' on tx_line [OK]

Common Mistakes:

• Confusing start bit with idle line '1'
• Assuming 'Z' or 'X' values appear
• Ignoring state conditions

4. Identify the error in this UART receiver process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if rx = '0' then
      data <= rx_data & rx;
    end if;
  end if;
end process;

medium

A. Missing reset condition for data register

B. Concatenation order is incorrect for data assembly

C. rx signal should be '1' to detect start bit

D. Process sensitivity list is incomplete

Solution

1. Step 1: Check process for reset handling

   The process lacks a reset condition to clear or initialize 'data', which is essential for reliable UART reception.

2. Step 2: Validate other parts

   Concatenation order and rx = '0' for start bit detection are correct; sensitivity list with clk is standard.

3. Final Answer:

   Missing reset condition for data register -> Option A

4. Quick Check:

   Reset needed to clear data = A [OK]

Hint: Always include reset in UART receiver process [OK]

Common Mistakes:

• Ignoring reset causes data corruption
• Thinking start bit is '1'
• Misunderstanding concatenation order

5. You want to design a UART transmitter in VHDL that sends 8-bit data with 1 start bit, 1 stop bit, and no parity. Which sequence correctly represents the bits sent on the tx line for data byte "10110011"?

hard

A. Start bit '0', data bits MSB first '10110011', stop bit '1'

B. Start bit '1', data bits MSB first '10110011', stop bit '0'

C. Start bit '0', data bits LSB first '11001101', stop bit '0'

D. Start bit '0', data bits LSB first '11001101', stop bit '1'

Solution

1. Step 1: Recall UART bit order and framing

   UART sends a start bit '0', then data bits least significant bit (LSB) first, then stop bit '1'.

2. Step 2: Convert data byte to LSB first sequence

   Data '10110011' MSB to LSB is bits 7 to 0. LSB first means sending '11001101'.

3. Step 3: Confirm start and stop bits

   Start bit is '0', stop bit is '1' as per UART standard.

4. Final Answer:

   Start bit '0', data bits LSB first '11001101', stop bit '1' -> Option D

5. Quick Check:

   UART sends start '0', LSB first, stop '1' = D [OK]

Hint: UART sends LSB first with start '0' and stop '1' bits [OK]

Common Mistakes:

• Sending MSB first instead of LSB first
• Using wrong stop bit value
• Confusing start bit as '1'