UART transmitter and receiver in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to define the UART transmitter entity name.

VHDL

entity [1] is
  Port ( clk : in std_logic;
         tx_start : in std_logic;
         tx_data : in std_logic_vector(7 downto 0);
         tx_serial : out std_logic;
         tx_busy : out std_logic);
end [1];

Drag options to blanks, or click blank then click option'

Auart_tx_rx

Buart_receiver

Cuart_tx

Duart_transmitter

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'uart_receiver' which is for the receiver entity.

Using 'uart_tx_rx' which combines transmitter and receiver.

The entity name for the UART transmitter is uart_tx.

2fill in blank

medium

Complete the code to assign the serial output in the UART transmitter process.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if tx_start = '1' then
      tx_serial <= [1];
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

A'0'

Btx_data(7)

C'1'

Dtx_data(0)

Attempts:

3 left

💡 Hint

Common Mistakes

Using the most significant bit tx_data(7) instead of the least significant bit.

Assigning constant '1' or '0' instead of data bits.

The UART transmitter sends the least significant bit first, so tx_data(0) is assigned to tx_serial.

3fill in blank

hard

Fix the error in the UART receiver process sensitivity list.

VHDL

process([1])
begin
  if rising_edge(clk) then
    -- UART receive logic
  end if;
end process;

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Aclk

Bclk, rx_serial

Crx_serial

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Adding rx_serial to the sensitivity list causing unintended behavior.

Using asynchronous signals in a synchronous process.

The process should be sensitive only to the clock signal clk for synchronous logic.

4fill in blank

hard

Fill both blanks to complete the UART transmitter state machine case statement.

VHDL

case state is
  when [1] =>
    if tx_start = '1' then
      state <= [2];
    end if;

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Aidle

Bstart_bit

Cstop_bit

Ddata_bits

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_bits or stop_bit as the initial state.

Swapping the order of states.

The transmitter starts in the idle state and moves to start_bit when transmission begins.

5fill in blank

hard

Fill all three blanks to complete the UART receiver data sampling condition.

VHDL

if rx_serial = [1] and bit_count = [2] then
  data_reg([3]) <= rx_serial;

Drag options to blanks, or click blank then click option'

A'0'

B7

Cbit_count

D'1'

Attempts:

3 left

💡 Hint

Common Mistakes

Using '1' instead of '0' for the start bit.

Using incorrect bit count values.

Assigning to a fixed index instead of bit_count.

The receiver samples the data bit when rx_serial is '0' (start bit), at bit count 7, and stores it in data_reg(bit_count).

Practice

1. What is the main role of the UART transmitter in a communication system?

easy

A. To send data bits serially with start and stop bits

B. To receive data bits and convert them to parallel form

C. To amplify the signal strength for transmission

D. To encrypt data before sending

Solution

1. Step 1: Understand UART transmitter function

   The UART transmitter converts parallel data into serial form and adds start and stop bits for synchronization.

2. Step 2: Differentiate transmitter from receiver roles

   The receiver listens and converts serial data back to parallel, so amplification or encryption is not the transmitter's main role.

3. Final Answer:

   To send data bits serially with start and stop bits -> Option A

4. Quick Check:

   Transmitter sends serial data = A [OK]

Hint: Remember: transmitter sends serial bits with start/stop [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking transmitter encrypts data
• Assuming transmitter amplifies signals

2. Which of the following is the correct VHDL port declaration for a UART receiver input line named rx?

easy

A. rx : out std_logic;

B. rx : inout std_logic_vector(7 downto 0);

C. rx : in std_logic;

D. rx : buffer std_logic_vector(7 downto 0);

Solution

1. Step 1: Identify direction of UART receiver input

   The receiver reads data from the input line, so the port direction must be 'in'.

2. Step 2: Check data type for single UART line

   UART input is a single bit line, so type is std_logic, not a vector.

3. Final Answer:

   rx : in std_logic; -> Option C

4. Quick Check:

   Receiver input is 'in std_logic' = C [OK]

Hint: Input lines use 'in std_logic' for single UART signals [OK]

Common Mistakes:

• Using 'out' instead of 'in' for receiver input
• Using std_logic_vector for single bit line
• Using 'buffer' or 'inout' incorrectly

3. Given this VHDL snippet for a UART transmitter process, what is the value of tx_line after sending the start bit?

process(clk)
begin
  if rising_edge(clk) then
    if state = IDLE then
      tx_line <= '1';
    elsif state = START_BIT then
      tx_line <= '0';
    end if;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. 'X'

Solution

1. Step 1: Analyze process behavior at START_BIT state

   When state equals START_BIT, the code sets tx_line to '0', representing the start bit.

2. Step 2: Confirm output value after start bit

   Since the start bit is '0', tx_line will be '0' during START_BIT state.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Start bit = '0' on tx_line = B [OK]

Hint: Start bit in UART is always '0' on tx_line [OK]

Common Mistakes:

• Confusing start bit with idle line '1'
• Assuming 'Z' or 'X' values appear
• Ignoring state conditions

4. Identify the error in this UART receiver process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if rx = '0' then
      data <= rx_data & rx;
    end if;
  end if;
end process;

medium

A. Missing reset condition for data register

B. Concatenation order is incorrect for data assembly

C. rx signal should be '1' to detect start bit

D. Process sensitivity list is incomplete

Solution

1. Step 1: Check process for reset handling

   The process lacks a reset condition to clear or initialize 'data', which is essential for reliable UART reception.

2. Step 2: Validate other parts

   Concatenation order and rx = '0' for start bit detection are correct; sensitivity list with clk is standard.

3. Final Answer:

   Missing reset condition for data register -> Option A

4. Quick Check:

   Reset needed to clear data = A [OK]

Hint: Always include reset in UART receiver process [OK]

Common Mistakes:

• Ignoring reset causes data corruption
• Thinking start bit is '1'
• Misunderstanding concatenation order

5. You want to design a UART transmitter in VHDL that sends 8-bit data with 1 start bit, 1 stop bit, and no parity. Which sequence correctly represents the bits sent on the tx line for data byte "10110011"?

hard

A. Start bit '0', data bits MSB first '10110011', stop bit '1'

B. Start bit '1', data bits MSB first '10110011', stop bit '0'

C. Start bit '0', data bits LSB first '11001101', stop bit '0'

D. Start bit '0', data bits LSB first '11001101', stop bit '1'

Solution

1. Step 1: Recall UART bit order and framing

   UART sends a start bit '0', then data bits least significant bit (LSB) first, then stop bit '1'.

2. Step 2: Convert data byte to LSB first sequence

   Data '10110011' MSB to LSB is bits 7 to 0. LSB first means sending '11001101'.

3. Step 3: Confirm start and stop bits

   Start bit is '0', stop bit is '1' as per UART standard.

4. Final Answer:

   Start bit '0', data bits LSB first '11001101', stop bit '1' -> Option D

5. Quick Check:

   UART sends start '0', LSB first, stop '1' = D [OK]

Hint: UART sends LSB first with start '0' and stop '1' bits [OK]

Common Mistakes:

• Sending MSB first instead of LSB first
• Using wrong stop bit value
• Confusing start bit as '1'