UART transmitter and receiver in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

UART Transmitter: Output Signal Timing

Given the UART transmitter code below, what is the output tx signal sequence for sending the byte 0x55 (binary 01010101) with 1 start bit, 8 data bits, no parity, and 1 stop bit?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uart_tx is
    Port ( clk : in STD_LOGIC;
           tx_start : in STD_LOGIC;
           tx_data : in STD_LOGIC_VECTOR (7 downto 0);
           tx : out STD_LOGIC;
           tx_busy : out STD_LOGIC);
end uart_tx;

architecture Behavioral of uart_tx is
    type state_type is (idle, start_bit, data_bits, stop_bit);
    signal state : state_type := idle;
    signal bit_cnt : integer range 0 to 7 := 0;
    signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            case state is
                when idle =>
                    tx <= '1';
                    tx_busy <= '0';
                    if tx_start = '1' then
                        shift_reg <= tx_data;
                        state <= start_bit;
                        tx_busy <= '1';
                    end if;
                when start_bit =>
                    tx <= '0';
                    state <= data_bits;
                    bit_cnt <= 0;
                when data_bits =>
                    tx <= shift_reg(bit_cnt);
                    if bit_cnt = 7 then
                        state <= stop_bit;
                    else
                        bit_cnt <= bit_cnt + 1;
                    end if;
                when stop_bit =>
                    tx <= '1';
                    state <= idle;
                    tx_busy <= '0';
            end case;
        end if;
    end process;
end Behavioral;

A '1' (idle), '0' (start), '0','1','0','1','0','1','0','1' (data bits LSB first), '1' (stop)

B '1' (idle), '0' (start), '1','0','1','0','1','0','1','0' (data bits LSB first), '1' (stop)

C '1' (idle), '1' (start), '0','1','0','1','0','1','0','1' (data bits LSB first), '0' (stop)

D '0' (idle), '1' (start), '1','0','1','0','1','0','1','0' (data bits LSB first), '1' (stop)

💡 Hint

Remember UART sends the start bit as 0, then data bits least significant bit first, then stop bit as 1.

The UART transmitter sends a 0 start bit, then the data bits from LSB to MSB. For 0x55 (binary 01010101), the bits sent are 1,0,1,0,1,0,1,0 LSB first. Finally, it sends a 1 stop bit.

❓ Predict Output

intermediate

UART Receiver: Data Output After Receiving Byte

Consider the UART receiver code snippet below. After receiving the byte 0xA3 (binary 10100011) with 1 start bit, 8 data bits, no parity, and 1 stop bit, what will be the value of rx_data?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity uart_rx is
    Port ( clk : in STD_LOGIC;
           rx : in STD_LOGIC;
           rx_data : out STD_LOGIC_VECTOR (7 downto 0);
           rx_ready : out STD_LOGIC);
end uart_rx;

architecture Behavioral of uart_rx is
    type state_type is (idle, start_bit, data_bits, stop_bit);
    signal state : state_type := idle;
    signal bit_cnt : integer range 0 to 7 := 0;
    signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            case state is
                when idle =>
                    rx_ready <= '0';
                    if rx = '0' then
                        state <= start_bit;
                    end if;
                when start_bit =>
                    if rx = '0' then
                        state <= data_bits;
                        bit_cnt <= 0;
                    else
                        state <= idle;
                    end if;
                when data_bits =>
                    shift_reg(bit_cnt) <= rx;
                    if bit_cnt = 7 then
                        state <= stop_bit;
                    else
                        bit_cnt <= bit_cnt + 1;
                    end if;
                when stop_bit =>
                    if rx = '1' then
                        rx_data <= shift_reg;
                        rx_ready <= '1';
                    end if;
                    state <= idle;
            end case;
        end if;
    end process;
end Behavioral;

A "00111010"

B "11000101"

C "10100011"

D "01011100"

💡 Hint

The receiver stores bits LSB first as they arrive after the start bit.

The UART receiver captures bits starting from the least significant bit. For 0xA3 (binary 10100011), the bits arrive as 1,1,0,0,0,1,0,1 LSB first, which matches 10100011 when stored in rx_data.

🔧 Debug

advanced

Identify the Error in UART Transmitter State Machine

Examine the UART transmitter state machine code below. Which option correctly identifies the error causing the transmitter to never send the stop bit?

VHDL

architecture Behavioral of uart_tx is
    type state_type is (idle, start_bit, data_bits, stop_bit);
    signal state : state_type := idle;
    signal bit_cnt : integer range 0 to 7 := 0;
    signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            case state is
                when idle =>
                    tx <= '1';
                    tx_busy <= '0';
                    if tx_start = '1' then
                        shift_reg <= tx_data;
                        state <= start_bit;
                        tx_busy <= '1';
                    end if;
                when start_bit =>
                    tx <= '0';
                    state <= data_bits;
                    bit_cnt <= 0;
                when data_bits =>
                    tx <= shift_reg(bit_cnt);
                    if bit_cnt = 7 then
                        state <= data_bits; -- Error here
                    else
                        bit_cnt <= bit_cnt + 1;
                    end if;
                when stop_bit =>
                    tx <= '1';
                    state <= idle;
                    tx_busy <= '0';
            end case;
        end if;
    end process;
end Behavioral;

A In state data_bits, when bit_cnt=7, state remains data_bits instead of moving to stop_bit.

B In state start_bit, tx is set to '0' instead of '1'.

C In state idle, tx_busy is never set to '1'.

D In state stop_bit, tx_busy is set to '1' instead of '0'.

💡 Hint

Check the transition after sending the last data bit.

The transmitter stays in data_bits state after sending the last bit because the code sets state <= data_bits; instead of state <= stop_bit;. This prevents sending the stop bit.

📝 Syntax

advanced

Syntax Error in UART Receiver Process

Which option contains the syntax error that will cause the UART receiver code below to fail compilation?

VHDL

architecture Behavioral of uart_rx is
    type state_type is (idle, start_bit, data_bits, stop_bit);
    signal state : state_type := idle;
    signal bit_cnt : integer range 0 to 7 := 0;
    signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            case state is
                when idle =>
                    rx_ready <= '0';
                    if rx = '0' then
                        state <= start_bit;
                    end if;
                when start_bit =>
                    if rx = '0' then
                        state <= data_bits;
                        bit_cnt <= 0;
                    else
                        state <= idle;
                    end if;
                when data_bits =>
                    shift_reg(bit_cnt) <= rx;
                    if bit_cnt = 7 then
                        state <= stop_bit;
                    else
                        bit_cnt <= bit_cnt + 1;
                    end if;
                when stop_bit =>
                    if rx = '1' then
                        rx_data <= shift_reg;
                        rx_ready <= '1';
                    end if;
                    state <= idle;
            end case;
        end if;
    end process;
end Behavioral;

A Use of 'case' statement without 'when others' clause.

B Incorrect signal assignment operator ':=' used instead of '<=' for 'bit_cnt'.

C Missing 'end process;' statement at the end of the process.

D Missing semicolon after 'state <= start_bit' in the idle state.

💡 Hint

Look carefully at each line ending in the idle state.

In VHDL, each statement must end with a semicolon. The line state <= start_bit in the idle state is missing a semicolon, causing a syntax error.

🚀 Application

expert

UART Full-Duplex Communication Timing Analysis

You have a UART transmitter and receiver both running at 9600 baud with 1 start bit, 8 data bits, no parity, and 1 stop bit. If the transmitter sends a continuous stream of bytes without delay, what is the minimum time interval between the start of one byte transmission and the start of the next byte reception at the receiver?

A Approximately 1.04 milliseconds

B Approximately 104 microseconds

C Approximately 10.4 milliseconds

D Approximately 0.52 milliseconds

💡 Hint

Calculate the time for one full UART frame (start + 8 data + stop bits) at 9600 baud.

At 9600 baud, each bit takes about 1/9600 ≈ 104.17 microseconds. One UART frame has 1 start + 8 data + 1 stop = 10 bits. So total time per byte is 10 × 104.17 µs ≈ 1.04 ms. This is the minimum interval between start bits of consecutive bytes.

Practice

1. What is the main role of the UART transmitter in a communication system?

easy

A. To send data bits serially with start and stop bits

B. To receive data bits and convert them to parallel form

C. To amplify the signal strength for transmission

D. To encrypt data before sending

Solution

1. Step 1: Understand UART transmitter function

   The UART transmitter converts parallel data into serial form and adds start and stop bits for synchronization.

2. Step 2: Differentiate transmitter from receiver roles

   The receiver listens and converts serial data back to parallel, so amplification or encryption is not the transmitter's main role.

3. Final Answer:

   To send data bits serially with start and stop bits -> Option A

4. Quick Check:

   Transmitter sends serial data = A [OK]

Hint: Remember: transmitter sends serial bits with start/stop [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking transmitter encrypts data
• Assuming transmitter amplifies signals

2. Which of the following is the correct VHDL port declaration for a UART receiver input line named rx?

easy

A. rx : out std_logic;

B. rx : inout std_logic_vector(7 downto 0);

C. rx : in std_logic;

D. rx : buffer std_logic_vector(7 downto 0);

Solution

1. Step 1: Identify direction of UART receiver input

   The receiver reads data from the input line, so the port direction must be 'in'.

2. Step 2: Check data type for single UART line

   UART input is a single bit line, so type is std_logic, not a vector.

3. Final Answer:

   rx : in std_logic; -> Option C

4. Quick Check:

   Receiver input is 'in std_logic' = C [OK]

Hint: Input lines use 'in std_logic' for single UART signals [OK]

Common Mistakes:

• Using 'out' instead of 'in' for receiver input
• Using std_logic_vector for single bit line
• Using 'buffer' or 'inout' incorrectly

3. Given this VHDL snippet for a UART transmitter process, what is the value of tx_line after sending the start bit?

process(clk)
begin
  if rising_edge(clk) then
    if state = IDLE then
      tx_line <= '1';
    elsif state = START_BIT then
      tx_line <= '0';
    end if;
  end if;
end process;

medium

A. '1'

B. '0'

C. 'Z'

D. 'X'

Solution

1. Step 1: Analyze process behavior at START_BIT state

   When state equals START_BIT, the code sets tx_line to '0', representing the start bit.

2. Step 2: Confirm output value after start bit

   Since the start bit is '0', tx_line will be '0' during START_BIT state.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Start bit = '0' on tx_line = B [OK]

Hint: Start bit in UART is always '0' on tx_line [OK]

Common Mistakes:

• Confusing start bit with idle line '1'
• Assuming 'Z' or 'X' values appear
• Ignoring state conditions

4. Identify the error in this UART receiver process snippet:

process(clk)
begin
  if rising_edge(clk) then
    if rx = '0' then
      data <= rx_data & rx;
    end if;
  end if;
end process;

medium

A. Missing reset condition for data register

B. Concatenation order is incorrect for data assembly

C. rx signal should be '1' to detect start bit

D. Process sensitivity list is incomplete

Solution

1. Step 1: Check process for reset handling

   The process lacks a reset condition to clear or initialize 'data', which is essential for reliable UART reception.

2. Step 2: Validate other parts

   Concatenation order and rx = '0' for start bit detection are correct; sensitivity list with clk is standard.

3. Final Answer:

   Missing reset condition for data register -> Option A

4. Quick Check:

   Reset needed to clear data = A [OK]

Hint: Always include reset in UART receiver process [OK]

Common Mistakes:

• Ignoring reset causes data corruption
• Thinking start bit is '1'
• Misunderstanding concatenation order

5. You want to design a UART transmitter in VHDL that sends 8-bit data with 1 start bit, 1 stop bit, and no parity. Which sequence correctly represents the bits sent on the tx line for data byte "10110011"?

hard

A. Start bit '0', data bits MSB first '10110011', stop bit '1'

B. Start bit '1', data bits MSB first '10110011', stop bit '0'

C. Start bit '0', data bits LSB first '11001101', stop bit '0'

D. Start bit '0', data bits LSB first '11001101', stop bit '1'

Solution

1. Step 1: Recall UART bit order and framing

   UART sends a start bit '0', then data bits least significant bit (LSB) first, then stop bit '1'.

2. Step 2: Convert data byte to LSB first sequence

   Data '10110011' MSB to LSB is bits 7 to 0. LSB first means sending '11001101'.

3. Step 3: Confirm start and stop bits

   Start bit is '0', stop bit is '1' as per UART standard.

4. Final Answer:

   Start bit '0', data bits LSB first '11001101', stop bit '1' -> Option D

5. Quick Check:

   UART sends start '0', LSB first, stop '1' = D [OK]

Hint: UART sends LSB first with start '0' and stop '1' bits [OK]

Common Mistakes:

• Sending MSB first instead of LSB first
• Using wrong stop bit value
• Confusing start bit as '1'