Synchronous FIFO design in VHDL - Step-by-Step Execution

Concept Flow - Synchronous FIFO design

Reset FIFO

↓

Write Pointer = 0

↓

Read Pointer = 0

↓

Check Write Enable?

No→Wait

Yes↓

Write Data at Write Pointer

↓

Increment Write Pointer

↓

Check Read Enable?

No→Wait

Yes↓

Read Data at Read Pointer

↓

Increment Read Pointer

↓

Repeat

The FIFO resets pointers, then on write enable writes data and increments write pointer, on read enable reads data and increments read pointer, repeating this cycle.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if rst = '1' then
      wr_ptr <= 0;
      rd_ptr <= 0;
    elsif wr_en = '1' then
      mem(wr_ptr) <= data_in;
      wr_ptr <= wr_ptr + 1;
    elsif rd_en = '1' then
      data_out <= mem(rd_ptr);
      rd_ptr <= rd_ptr + 1;
    end if;
  end if;
end process;

This process resets pointers on reset, writes data on write enable, and reads data on read enable synchronously with clock.

Execution Table

Step	clk rising_edge	rst	wr_en	rd_en	wr_ptr	rd_ptr	Action	Output
1	Yes	1	0	0	0	0	Reset pointers	-
2	Yes	0	1	0	0	0	Write data at wr_ptr=0; wr_ptr=1	-
3	Yes	0	1	0	1	0	Write data at wr_ptr=1; wr_ptr=2	-
4	Yes	0	0	1	2	0	Read data at rd_ptr=0; rd_ptr=1	data_out=mem[0]
5	Yes	0	0	1	2	1	Read data at rd_ptr=1; rd_ptr=2	data_out=mem[1]
6	Yes	0	0	0	2	2	No write/read; pointers unchanged	-
7	No	0	1	0	2	2	No clock edge; no action	-

💡 No clock edge or reset disables actions; pointers unchanged.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7
wr_ptr	0	0	1	2	2	2	2	2
rd_ptr	0	0	0	0	1	2	2	2
data_out	-	-	-	-	mem[0]	mem[1]	mem[1]	mem[1]

Key Moments - 3 Insights

Why does the write pointer increment only when wr_en is '1' and not on every clock?

Because in the execution_table rows 2 and 3, wr_ptr increments only when wr_en='1', showing data is written only when enabled.

Why does the read pointer not increment when rd_en is '0'?

As seen in step 6, when rd_en='0', rd_ptr stays the same, so no read occurs without enable.

What happens if both wr_en and rd_en are '1' at the same clock?

In this design, the elsif structure prioritizes write over read, so only write happens; read is skipped this cycle.

Visual Quiz - 3 Questions

Look at the execution_table at step 4, what is the value of rd_ptr after the step?

A 1

B 2

C 0

D 3

💡 Hint

Check the 'rd_ptr' column in execution_table row for step 4.

At which step does the write pointer first increment?

A Step 1

B Step 4

C Step 2

D Step 6

💡 Hint

Look at wr_ptr changes in variable_tracker and execution_table wr_ptr column.

If rst is '1', what happens to wr_ptr and rd_ptr?

A Both increment by 1

B Both reset to 0

C Only wr_ptr resets

D Only rd_ptr resets

💡 Hint

See step 1 in execution_table where rst='1' and pointers reset.

Concept Snapshot

Synchronous FIFO design in VHDL:
- Use clock rising edge to sync operations
- Reset sets write/read pointers to 0
- On wr_en='1', write data and increment write pointer
- On rd_en='1', read data and increment read pointer
- Write has priority if both enabled
- Pointers wrap around FIFO size (not shown here)

Full Transcript

This visual execution trace shows a synchronous FIFO design in VHDL. The FIFO resets write and read pointers to zero on reset. When the clock rises, if write enable is active, data is written at the write pointer location and the write pointer increments. If read enable is active (and write enable is not), data is read from the read pointer location and the read pointer increments. If neither enable is active, pointers stay the same. The write pointer increments only on write enable, and the read pointer increments only on read enable. If both enables are active, write takes priority. This cycle repeats every clock rising edge.

Practice

1. What is the main purpose of a synchronous FIFO in VHDL?

easy

A. To perform asynchronous data transfers between different clock domains

B. To store data in order using a single clock signal

C. To generate clock signals for other components

D. To convert analog signals to digital

Solution

1. Step 1: Understand FIFO functionality

   A FIFO (First-In-First-Out) stores data in the order it arrives.

2. Step 2: Identify synchronous aspect

   A synchronous FIFO uses one clock to control both read and write operations.

3. Final Answer:

   To store data in order using a single clock signal -> Option B

4. Quick Check:

   Synchronous FIFO = single clock storage [OK]

Hint: Remember FIFO means first-in, first-out with one clock [OK]

Common Mistakes:

• Confusing synchronous with asynchronous FIFO
• Thinking FIFO generates clocks
• Mixing FIFO with analog-to-digital conversion

2. Which VHDL signal type is typically used for the FIFO write pointer in a synchronous FIFO?

easy

A. std_logic_vector

B. integer

C. boolean

D. real

Solution

1. Step 1: Identify pointer representation

   Write pointers are usually binary counters represented as vectors.

2. Step 2: Choose appropriate type

   std_logic_vector is used to represent binary numbers in VHDL.

3. Final Answer:

   std_logic_vector -> Option A

4. Quick Check:

   Write pointer = std_logic_vector [OK]

Hint: Pointers are binary, so use std_logic_vector [OK]

Common Mistakes:

• Using integer which is less hardware-friendly
• Using boolean which can't count multiple bits
• Using real which is for floating-point numbers

3. Given a synchronous FIFO with depth 4, write pointer at "10" (binary 2), read pointer at "01" (binary 1), and count = 2, what happens if write enable is high and FIFO is not full?

medium

A. Write pointer resets to 0 without writing data

B. Data is written at position 1, write pointer increments to 2, count becomes 3

C. Data is not written because FIFO is full

D. Data is written at position 2, write pointer increments to 3, count becomes 3

Solution

1. Step 1: Check FIFO status

   Count is 2, depth is 4, so FIFO is not full.

2. Step 2: Write operation effect

   Data writes at write pointer position 2, pointer increments to 3, count increments to 3.

3. Final Answer:

   Data is written at position 2, write pointer increments to 3, count becomes 3 -> Option D

4. Quick Check:

   Write enabled + not full = write and increment [OK]

Hint: Write pointer points where data writes; count increments if not full [OK]

Common Mistakes:

• Writing at read pointer instead of write pointer
• Not incrementing count after write
• Assuming FIFO is full incorrectly

4. Identify the error in this VHDL snippet for a synchronous FIFO write process:

process(clk)
begin
  if rising_edge(clk) then
    if (write_enable = '1') and (not full) then
      fifo_mem(write_ptr) <= data_in;
      write_ptr <= write_ptr + 1;
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. write_ptr and count signals are not wrapped around FIFO depth

B. Missing reset condition for write_ptr

C. Data is written even when FIFO is full

D. Process is not sensitive to write_enable

Solution

1. Step 1: Analyze pointer increment logic

   write_ptr increments without wrapping back to zero at FIFO depth limit.

2. Step 2: Understand FIFO pointer behavior

   Write pointer must wrap around to zero after reaching max depth to avoid overflow.

3. Final Answer:

   write_ptr and count signals are not wrapped around FIFO depth -> Option A

4. Quick Check:

   Pointer wrap-around needed to avoid overflow [OK]

Hint: Always wrap pointers modulo FIFO depth [OK]

Common Mistakes:

• Ignoring pointer wrap-around causing overflow
• Assuming reset is mandatory in this snippet
• Confusing sensitivity list with process behavior

5. You want to design a synchronous FIFO with depth 8 and 4-bit data width. Which of the following VHDL design choices correctly ensures no data overwrite and proper empty/full detection?

hard

A. Use 3-bit write and read pointers with a count signal; check full when count = 7 and empty when count = 0

B. Use 4-bit write and read pointers without count; check full when write_ptr = read_ptr and empty when write_ptr = read_ptr

C. Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr

D. Use 4-bit write and read pointers with count; check full when count = 15 and empty when count = 0

Solution

1. Step 1: Determine pointer size

   Depth 8 requires 3-bit pointers (since 2^3=8).

2. Step 2: Understand full/empty detection without count

   Full when write pointer is one less than read pointer (circular), empty when equal.

3. Step 3: Evaluate options

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr correctly uses 3-bit pointers without count and proper full/empty logic.

4. Final Answer:

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr -> Option C

5. Quick Check:

   Pointer wrap + compare = full/empty detection [OK]

Hint: Use pointer difference for full/empty without count [OK]

Common Mistakes:

• Using wrong pointer size for FIFO depth
• Confusing full and empty conditions
• Using count with incorrect max value