Synchronous FIFO design in VHDL - Mini Project: Build & Apply

Synchronous FIFO Design in VHDL

📖 Scenario: You are designing a simple hardware component called a FIFO (First-In-First-Out) buffer. This buffer stores data temporarily and outputs it in the same order it was received. This is useful in many digital systems where data needs to be queued and processed in order.

🎯 Goal: Build a synchronous FIFO in VHDL that can store 4 data elements of 8 bits each. You will create the data storage, control signals, and logic to write and read data in order.

📋 What You'll Learn

Create a memory array to hold 4 elements of 8-bit data

Add write and read pointers to track positions

Implement logic to write data when enabled and not full

Implement logic to read data when enabled and not empty

Output the data read from the FIFO

💡 Why This Matters

🌍 Real World

FIFOs are used in hardware designs to buffer data between components running at different speeds, such as between a processor and a peripheral device.

💼 Career

Understanding FIFO design is important for FPGA and ASIC engineers working on digital system design and verification.

1

Create FIFO memory and pointers

Create a signal called fifo_mem as an array of 4 elements, each 8 bits wide. Also create two signals called write_ptr and read_ptr as 2-bit unsigned integers initialized to 0.

VHDL

-- Your code here

Hint

Use an array type for fifo_mem and unsigned type for pointers from ieee.numeric_std.

2

Add full and empty status signals

Create two signals called full and empty of type std_logic. Add logic inside a process triggered by clk and rst to set full when the next write pointer equals the read pointer, and empty when the write pointer equals the read pointer.

VHDL

    process(clk, rst)
    begin
        if rst = '1' then
            write_ptr  '0');
            read_ptr  '0');
            full_sig <= '0';
            empty_sig <= '1';
        elsif rising_edge(clk) then
            -- Add logic to update full_sig and empty_sig
            -- Your code here
        end if;
    end process;

Hint

Use modulo 4 arithmetic to check if the FIFO is full. Compare pointers to check if empty.

3

Implement write and read logic

Inside the same process, add logic to write data_in to fifo_mem at write_ptr when write_en is '1' and FIFO is not full. Also, increment write_ptr in this case. Similarly, if read_en is '1' and FIFO is not empty, increment read_ptr.

VHDL

            -- Your code here
            -- Add write logic: if write_en = '1' and not full, write data_in to fifo_mem at write_ptr and increment write_ptr
            -- Add read logic: if read_en = '1' and not empty, increment read_ptr

Hint

Use to_integer to index the array. Increment pointers with modulo 4.

4

Output the data from FIFO

Assign data_out to the value stored in fifo_mem at read_ptr. This should reflect the current data to be read from the FIFO.

VHDL

    -- Your code here
    -- Assign data_out to fifo_mem at read_ptr

Hint

Assign data_out outside the process using the current read_ptr.

Practice

1. What is the main purpose of a synchronous FIFO in VHDL?

easy

A. To perform asynchronous data transfers between different clock domains

B. To store data in order using a single clock signal

C. To generate clock signals for other components

D. To convert analog signals to digital

Solution

1. Step 1: Understand FIFO functionality

   A FIFO (First-In-First-Out) stores data in the order it arrives.

2. Step 2: Identify synchronous aspect

   A synchronous FIFO uses one clock to control both read and write operations.

3. Final Answer:

   To store data in order using a single clock signal -> Option B

4. Quick Check:

   Synchronous FIFO = single clock storage [OK]

Hint: Remember FIFO means first-in, first-out with one clock [OK]

Common Mistakes:

• Confusing synchronous with asynchronous FIFO
• Thinking FIFO generates clocks
• Mixing FIFO with analog-to-digital conversion

2. Which VHDL signal type is typically used for the FIFO write pointer in a synchronous FIFO?

easy

A. std_logic_vector

B. integer

C. boolean

D. real

Solution

1. Step 1: Identify pointer representation

   Write pointers are usually binary counters represented as vectors.

2. Step 2: Choose appropriate type

   std_logic_vector is used to represent binary numbers in VHDL.

3. Final Answer:

   std_logic_vector -> Option A

4. Quick Check:

   Write pointer = std_logic_vector [OK]

Hint: Pointers are binary, so use std_logic_vector [OK]

Common Mistakes:

• Using integer which is less hardware-friendly
• Using boolean which can't count multiple bits
• Using real which is for floating-point numbers

3. Given a synchronous FIFO with depth 4, write pointer at "10" (binary 2), read pointer at "01" (binary 1), and count = 2, what happens if write enable is high and FIFO is not full?

medium

A. Write pointer resets to 0 without writing data

B. Data is written at position 1, write pointer increments to 2, count becomes 3

C. Data is not written because FIFO is full

D. Data is written at position 2, write pointer increments to 3, count becomes 3

Solution

1. Step 1: Check FIFO status

   Count is 2, depth is 4, so FIFO is not full.

2. Step 2: Write operation effect

   Data writes at write pointer position 2, pointer increments to 3, count increments to 3.

3. Final Answer:

   Data is written at position 2, write pointer increments to 3, count becomes 3 -> Option D

4. Quick Check:

   Write enabled + not full = write and increment [OK]

Hint: Write pointer points where data writes; count increments if not full [OK]

Common Mistakes:

• Writing at read pointer instead of write pointer
• Not incrementing count after write
• Assuming FIFO is full incorrectly

4. Identify the error in this VHDL snippet for a synchronous FIFO write process:

process(clk)
begin
  if rising_edge(clk) then
    if (write_enable = '1') and (not full) then
      fifo_mem(write_ptr) <= data_in;
      write_ptr <= write_ptr + 1;
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. write_ptr and count signals are not wrapped around FIFO depth

B. Missing reset condition for write_ptr

C. Data is written even when FIFO is full

D. Process is not sensitive to write_enable

Solution

1. Step 1: Analyze pointer increment logic

   write_ptr increments without wrapping back to zero at FIFO depth limit.

2. Step 2: Understand FIFO pointer behavior

   Write pointer must wrap around to zero after reaching max depth to avoid overflow.

3. Final Answer:

   write_ptr and count signals are not wrapped around FIFO depth -> Option A

4. Quick Check:

   Pointer wrap-around needed to avoid overflow [OK]

Hint: Always wrap pointers modulo FIFO depth [OK]

Common Mistakes:

• Ignoring pointer wrap-around causing overflow
• Assuming reset is mandatory in this snippet
• Confusing sensitivity list with process behavior

5. You want to design a synchronous FIFO with depth 8 and 4-bit data width. Which of the following VHDL design choices correctly ensures no data overwrite and proper empty/full detection?

hard

A. Use 3-bit write and read pointers with a count signal; check full when count = 7 and empty when count = 0

B. Use 4-bit write and read pointers without count; check full when write_ptr = read_ptr and empty when write_ptr = read_ptr

C. Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr

D. Use 4-bit write and read pointers with count; check full when count = 15 and empty when count = 0

Solution

1. Step 1: Determine pointer size

   Depth 8 requires 3-bit pointers (since 2^3=8).

2. Step 2: Understand full/empty detection without count

   Full when write pointer is one less than read pointer (circular), empty when equal.

3. Step 3: Evaluate options

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr correctly uses 3-bit pointers without count and proper full/empty logic.

4. Final Answer:

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr -> Option C

5. Quick Check:

   Pointer wrap + compare = full/empty detection [OK]

Hint: Use pointer difference for full/empty without count [OK]

Common Mistakes:

• Using wrong pointer size for FIFO depth
• Confusing full and empty conditions
• Using count with incorrect max value