Synchronous FIFO design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of FIFO write and read pointers

Consider a synchronous FIFO with depth 4. The write pointer (wr_ptr) and read pointer (rd_ptr) are 2-bit counters. After writing 3 data items and reading 1, what are the values of wr_ptr and rd_ptr?

VHDL

signal wr_ptr : std_logic_vector(1 downto 0) := "00";
signal rd_ptr : std_logic_vector(1 downto 0) := "00";

-- After writing 3 times:
wr_ptr <= std_logic_vector(unsigned(wr_ptr) + 1);
wr_ptr <= std_logic_vector(unsigned(wr_ptr) + 1);
wr_ptr <= std_logic_vector(unsigned(wr_ptr) + 1);

-- After reading 1 time:
rd_ptr <= std_logic_vector(unsigned(rd_ptr) + 1);

A wr_ptr = "11", rd_ptr = "10"

B wr_ptr = "11", rd_ptr = "01"

C wr_ptr = "10", rd_ptr = "01"

D wr_ptr = "10", rd_ptr = "10"

💡 Hint

Count how many times each pointer increments and remember they are 2-bit counters.

Writing 3 times increments wr_ptr from 00 to 11 (0->1->2->3). Reading once increments rd_ptr from 00 to 01.

🧠 Conceptual

intermediate

FIFO full condition detection

In a synchronous FIFO design, which condition correctly indicates the FIFO is full?

A When wr_ptr = (rd_ptr + 1) mod depth

B When wr_ptr = rd_ptr

C When (wr_ptr + 1) mod depth = rd_ptr

D When wr_ptr > rd_ptr

💡 Hint

Think about how the write pointer catches up to the read pointer in a circular buffer.

The FIFO is full when the write pointer is one position behind the read pointer in a circular manner, meaning (wr_ptr + 1) mod depth equals rd_ptr.

🔧 Debug

advanced

Identify the error in FIFO empty flag logic

Given the following VHDL code snippet for empty flag, what is the error?

VHDL

empty <= '1' when wr_ptr = rd_ptr else '0';

-- wr_ptr and rd_ptr are std_logic_vector(2 downto 0)

A Should convert std_logic_vector to unsigned before comparison

B Empty flag logic is correct and will work as intended

C Comparing std_logic_vector directly causes a runtime error

D Empty flag should be '0' when pointers are equal

💡 Hint

Think about how VHDL compares vectors and the need for numeric types.

In VHDL, comparing std_logic_vector directly is allowed but may not reflect numeric comparison. For pointer arithmetic and comparison, converting to unsigned is safer and clearer.

📝 Syntax

advanced

Syntax error in FIFO write process

Which option contains the correct VHDL syntax for a synchronous FIFO write process triggered on rising clock edge?

A

process(clk)
begin
  if rising_edge(clk) then
    if write_enable = '1' then
      mem(to_integer(unsigned(wr_ptr))) <= data_in;
      wr_ptr <= wr_ptr + 1;
    end if;
  end if;
end process;

B

process(clk)
begin
  if clk'event and clk = '1' then
    if write_enable = '1' then
      mem(to_integer(unsigned(wr_ptr))) <= data_in;
      wr_ptr <= std_logic_vector(unsigned(wr_ptr) + 1);
    end if;
  end if;
end process;

C

process(clk)
begin
  if rising_edge(clk) then
    if write_enable = 1 then
      mem(to_integer(unsigned(wr_ptr))) <= data_in;
      wr_ptr <= std_logic_vector(unsigned(wr_ptr) + 1);
    end if;
  end if;
end process;

D

process(clk)
begin
  if rising_edge(clk) then
    if write_enable = '1' then
      mem(to_integer(unsigned(wr_ptr))) <= data_in;
      wr_ptr <= std_logic_vector(unsigned(wr_ptr) + 1);
    end if;
  end if;
end process;

💡 Hint

Check the correct way to detect rising edge and compare std_logic signals.

Option D uses the correct rising_edge function and compares write_enable to '1' (std_logic). Option D uses older style but is valid. Option D compares write_enable to integer 1 (wrong). Option D tries to add integer to std_logic_vector directly (invalid).

🚀 Application

expert

Calculate FIFO occupancy count

In a synchronous FIFO with depth 8, write pointer wr_ptr and read pointer rd_ptr are 3-bit unsigned counters. Which VHDL expression correctly calculates the number of stored items (occupancy)?

A occupancy <= std_logic_vector((unsigned(wr_ptr) - unsigned(rd_ptr)) mod 8);

B occupancy <= std_logic_vector(unsigned(wr_ptr) - unsigned(rd_ptr));

C occupancy <= std_logic_vector((unsigned(rd_ptr) - unsigned(wr_ptr)) mod 8);

D occupancy <= std_logic_vector(unsigned(rd_ptr) + unsigned(wr_ptr));

💡 Hint

Think about pointer wrap-around and modulo arithmetic for circular buffers.

The occupancy is the difference between write and read pointers modulo the FIFO depth. This handles wrap-around correctly.

Practice

1. What is the main purpose of a synchronous FIFO in VHDL?

easy

A. To perform asynchronous data transfers between different clock domains

B. To store data in order using a single clock signal

C. To generate clock signals for other components

D. To convert analog signals to digital

Solution

1. Step 1: Understand FIFO functionality

   A FIFO (First-In-First-Out) stores data in the order it arrives.

2. Step 2: Identify synchronous aspect

   A synchronous FIFO uses one clock to control both read and write operations.

3. Final Answer:

   To store data in order using a single clock signal -> Option B

4. Quick Check:

   Synchronous FIFO = single clock storage [OK]

Hint: Remember FIFO means first-in, first-out with one clock [OK]

Common Mistakes:

• Confusing synchronous with asynchronous FIFO
• Thinking FIFO generates clocks
• Mixing FIFO with analog-to-digital conversion

2. Which VHDL signal type is typically used for the FIFO write pointer in a synchronous FIFO?

easy

A. std_logic_vector

B. integer

C. boolean

D. real

Solution

1. Step 1: Identify pointer representation

   Write pointers are usually binary counters represented as vectors.

2. Step 2: Choose appropriate type

   std_logic_vector is used to represent binary numbers in VHDL.

3. Final Answer:

   std_logic_vector -> Option A

4. Quick Check:

   Write pointer = std_logic_vector [OK]

Hint: Pointers are binary, so use std_logic_vector [OK]

Common Mistakes:

• Using integer which is less hardware-friendly
• Using boolean which can't count multiple bits
• Using real which is for floating-point numbers

3. Given a synchronous FIFO with depth 4, write pointer at "10" (binary 2), read pointer at "01" (binary 1), and count = 2, what happens if write enable is high and FIFO is not full?

medium

A. Write pointer resets to 0 without writing data

B. Data is written at position 1, write pointer increments to 2, count becomes 3

C. Data is not written because FIFO is full

D. Data is written at position 2, write pointer increments to 3, count becomes 3

Solution

1. Step 1: Check FIFO status

   Count is 2, depth is 4, so FIFO is not full.

2. Step 2: Write operation effect

   Data writes at write pointer position 2, pointer increments to 3, count increments to 3.

3. Final Answer:

   Data is written at position 2, write pointer increments to 3, count becomes 3 -> Option D

4. Quick Check:

   Write enabled + not full = write and increment [OK]

Hint: Write pointer points where data writes; count increments if not full [OK]

Common Mistakes:

• Writing at read pointer instead of write pointer
• Not incrementing count after write
• Assuming FIFO is full incorrectly

4. Identify the error in this VHDL snippet for a synchronous FIFO write process:

process(clk)
begin
  if rising_edge(clk) then
    if (write_enable = '1') and (not full) then
      fifo_mem(write_ptr) <= data_in;
      write_ptr <= write_ptr + 1;
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. write_ptr and count signals are not wrapped around FIFO depth

B. Missing reset condition for write_ptr

C. Data is written even when FIFO is full

D. Process is not sensitive to write_enable

Solution

1. Step 1: Analyze pointer increment logic

   write_ptr increments without wrapping back to zero at FIFO depth limit.

2. Step 2: Understand FIFO pointer behavior

   Write pointer must wrap around to zero after reaching max depth to avoid overflow.

3. Final Answer:

   write_ptr and count signals are not wrapped around FIFO depth -> Option A

4. Quick Check:

   Pointer wrap-around needed to avoid overflow [OK]

Hint: Always wrap pointers modulo FIFO depth [OK]

Common Mistakes:

• Ignoring pointer wrap-around causing overflow
• Assuming reset is mandatory in this snippet
• Confusing sensitivity list with process behavior

5. You want to design a synchronous FIFO with depth 8 and 4-bit data width. Which of the following VHDL design choices correctly ensures no data overwrite and proper empty/full detection?

hard

A. Use 3-bit write and read pointers with a count signal; check full when count = 7 and empty when count = 0

B. Use 4-bit write and read pointers without count; check full when write_ptr = read_ptr and empty when write_ptr = read_ptr

C. Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr

D. Use 4-bit write and read pointers with count; check full when count = 15 and empty when count = 0

Solution

1. Step 1: Determine pointer size

   Depth 8 requires 3-bit pointers (since 2^3=8).

2. Step 2: Understand full/empty detection without count

   Full when write pointer is one less than read pointer (circular), empty when equal.

3. Step 3: Evaluate options

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr correctly uses 3-bit pointers without count and proper full/empty logic.

4. Final Answer:

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr -> Option C

5. Quick Check:

   Pointer wrap + compare = full/empty detection [OK]

Hint: Use pointer difference for full/empty without count [OK]

Common Mistakes:

• Using wrong pointer size for FIFO depth
• Confusing full and empty conditions
• Using count with incorrect max value