Synchronous FIFO design in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What does FIFO stand for in digital design?

FIFO stands for First In, First Out. It means the first data stored is the first data retrieved, like a queue.

beginner

In a synchronous FIFO, what clock signal controls the read and write operations?

A single clock signal controls both read and write operations, ensuring all actions happen in sync.

intermediate

Why do we use pointers in FIFO design?

Pointers keep track of where to write new data and where to read existing data in the memory buffer.

beginner

What is the purpose of the 'full' and 'empty' flags in a FIFO?

The full flag tells when the FIFO cannot accept more data, and the empty flag tells when there is no data to read.

intermediate

How does a synchronous FIFO avoid data corruption during simultaneous read and write?

By using a single clock and carefully updating read and write pointers only on clock edges, it ensures no overlap or data loss.

In a synchronous FIFO, which signal controls the timing of data storage and retrieval?

A A single clock signal

B Separate clocks for read and write

C An asynchronous reset

D A data enable signal

A synchronous FIFO uses one clock signal to control both read and write operations, keeping them in sync.

What does the 'empty' flag indicate in a FIFO?

A No data available to read

B FIFO is full

C Write pointer equals read pointer

D Memory overflow

The 'empty' flag means there is no data to read from the FIFO.

Why are pointers important in FIFO design?

A To store data values

B To reset the FIFO

C To generate clock signals

D To track read and write positions

Pointers track where to read and write data in the FIFO memory.

What happens when the FIFO 'full' flag is set?

A Data can still be written

B FIFO is empty

C No more data can be written until space frees up

D Read pointer resets

When 'full' is set, the FIFO cannot accept new data until some is read out.

Which VHDL construct is commonly used to update FIFO pointers on clock edges?

A Concurrent signal assignment

B Process with sensitivity to clock

C Function call

D Wait statement

A process sensitive to the clock edge updates pointers synchronously.

Explain how a synchronous FIFO manages data flow using read and write pointers.

Think about how the FIFO knows where to put new data and where to get data from.

Describe the role of 'full' and 'empty' flags in preventing errors in FIFO operation.

Consider what happens if you try to write when full or read when empty.

Practice

1. What is the main purpose of a synchronous FIFO in VHDL?

easy

A. To perform asynchronous data transfers between different clock domains

B. To store data in order using a single clock signal

C. To generate clock signals for other components

D. To convert analog signals to digital

Solution

1. Step 1: Understand FIFO functionality

   A FIFO (First-In-First-Out) stores data in the order it arrives.

2. Step 2: Identify synchronous aspect

   A synchronous FIFO uses one clock to control both read and write operations.

3. Final Answer:

   To store data in order using a single clock signal -> Option B

4. Quick Check:

   Synchronous FIFO = single clock storage [OK]

Hint: Remember FIFO means first-in, first-out with one clock [OK]

Common Mistakes:

• Confusing synchronous with asynchronous FIFO
• Thinking FIFO generates clocks
• Mixing FIFO with analog-to-digital conversion

2. Which VHDL signal type is typically used for the FIFO write pointer in a synchronous FIFO?

easy

A. std_logic_vector

B. integer

C. boolean

D. real

Solution

1. Step 1: Identify pointer representation

   Write pointers are usually binary counters represented as vectors.

2. Step 2: Choose appropriate type

   std_logic_vector is used to represent binary numbers in VHDL.

3. Final Answer:

   std_logic_vector -> Option A

4. Quick Check:

   Write pointer = std_logic_vector [OK]

Hint: Pointers are binary, so use std_logic_vector [OK]

Common Mistakes:

• Using integer which is less hardware-friendly
• Using boolean which can't count multiple bits
• Using real which is for floating-point numbers

3. Given a synchronous FIFO with depth 4, write pointer at "10" (binary 2), read pointer at "01" (binary 1), and count = 2, what happens if write enable is high and FIFO is not full?

medium

A. Write pointer resets to 0 without writing data

B. Data is written at position 1, write pointer increments to 2, count becomes 3

C. Data is not written because FIFO is full

D. Data is written at position 2, write pointer increments to 3, count becomes 3

Solution

1. Step 1: Check FIFO status

   Count is 2, depth is 4, so FIFO is not full.

2. Step 2: Write operation effect

   Data writes at write pointer position 2, pointer increments to 3, count increments to 3.

3. Final Answer:

   Data is written at position 2, write pointer increments to 3, count becomes 3 -> Option D

4. Quick Check:

   Write enabled + not full = write and increment [OK]

Hint: Write pointer points where data writes; count increments if not full [OK]

Common Mistakes:

• Writing at read pointer instead of write pointer
• Not incrementing count after write
• Assuming FIFO is full incorrectly

4. Identify the error in this VHDL snippet for a synchronous FIFO write process:

process(clk)
begin
  if rising_edge(clk) then
    if (write_enable = '1') and (not full) then
      fifo_mem(write_ptr) <= data_in;
      write_ptr <= write_ptr + 1;
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. write_ptr and count signals are not wrapped around FIFO depth

B. Missing reset condition for write_ptr

C. Data is written even when FIFO is full

D. Process is not sensitive to write_enable

Solution

1. Step 1: Analyze pointer increment logic

   write_ptr increments without wrapping back to zero at FIFO depth limit.

2. Step 2: Understand FIFO pointer behavior

   Write pointer must wrap around to zero after reaching max depth to avoid overflow.

3. Final Answer:

   write_ptr and count signals are not wrapped around FIFO depth -> Option A

4. Quick Check:

   Pointer wrap-around needed to avoid overflow [OK]

Hint: Always wrap pointers modulo FIFO depth [OK]

Common Mistakes:

• Ignoring pointer wrap-around causing overflow
• Assuming reset is mandatory in this snippet
• Confusing sensitivity list with process behavior

5. You want to design a synchronous FIFO with depth 8 and 4-bit data width. Which of the following VHDL design choices correctly ensures no data overwrite and proper empty/full detection?

hard

A. Use 3-bit write and read pointers with a count signal; check full when count = 7 and empty when count = 0

B. Use 4-bit write and read pointers without count; check full when write_ptr = read_ptr and empty when write_ptr = read_ptr

C. Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr

D. Use 4-bit write and read pointers with count; check full when count = 15 and empty when count = 0

Solution

1. Step 1: Determine pointer size

   Depth 8 requires 3-bit pointers (since 2^3=8).

2. Step 2: Understand full/empty detection without count

   Full when write pointer is one less than read pointer (circular), empty when equal.

3. Step 3: Evaluate options

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr correctly uses 3-bit pointers without count and proper full/empty logic.

4. Final Answer:

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr -> Option C

5. Quick Check:

   Pointer wrap + compare = full/empty detection [OK]

Hint: Use pointer difference for full/empty without count [OK]

Common Mistakes:

• Using wrong pointer size for FIFO depth
• Confusing full and empty conditions
• Using count with incorrect max value