Synchronous FIFO design in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a FIFO memory array of 16 elements, each 8 bits wide.

VHDL

type fifo_mem is array (0 to 15) of std_logic_vector([1] downto 0);

Drag options to blanks, or click blank then click option'

A15

B7

C8

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using 8 downto 0 which is 9 bits.

Using 15 downto 0 which is 16 bits.

The FIFO stores 8-bit data, so the index goes from 7 downto 0.

2fill in blank

medium

Complete the code to increment the write pointer with wrap-around in a 4-bit pointer.

VHDL

write_ptr <= (write_ptr + 1) mod [1];

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A8

B4

C16

D32

Attempts:

3 left

💡 Hint

Common Mistakes

Using modulo 4 which is too small.

Using modulo 8 which is half the size.

The FIFO depth is 16, so the pointer wraps around modulo 16.

3fill in blank

hard

Fix the error in the FIFO full condition check.

VHDL

fifo_full <= '1' when (write_ptr = [1]) else '0';

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Aread_ptr + 1

Bwrite_ptr

Cread_ptr - 1

Dread_ptr

Attempts:

3 left

💡 Hint

Common Mistakes

Comparing write_ptr to read_ptr directly.

Comparing write_ptr to write_ptr.

The FIFO is full when the write pointer is one less than the read pointer (with wrap-around).

4fill in blank

hard

Fill both blanks to complete the process sensitivity list and reset condition.

VHDL

process([1], [2])
begin
  if reset = '1' then
    write_ptr <= (others => '0');
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cwrite_ptr

Ddata_in

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_in or write_ptr in sensitivity list unnecessarily.

The process must be sensitive to clock and reset signals.

5fill in blank

hard

Fill all three blanks to complete the FIFO write operation inside the clocked process.

VHDL

if rising_edge([1]) then
  if write_enable = '1' and fifo_full = '0' then
    fifo_mem([2]) <= [3];
  end if;
end if;

Drag options to blanks, or click blank then click option'

Aclk

Bwrite_ptr

Cdata_in

Dread_ptr

Attempts:

3 left

💡 Hint

Common Mistakes

Using read_ptr instead of write_ptr for memory index.

Using wrong signal for clock edge.

The write operation happens on clock rising edge, writing data_in to fifo_mem at write_ptr.

Practice

1. What is the main purpose of a synchronous FIFO in VHDL?

easy

A. To perform asynchronous data transfers between different clock domains

B. To store data in order using a single clock signal

C. To generate clock signals for other components

D. To convert analog signals to digital

Solution

1. Step 1: Understand FIFO functionality

   A FIFO (First-In-First-Out) stores data in the order it arrives.

2. Step 2: Identify synchronous aspect

   A synchronous FIFO uses one clock to control both read and write operations.

3. Final Answer:

   To store data in order using a single clock signal -> Option B

4. Quick Check:

   Synchronous FIFO = single clock storage [OK]

Hint: Remember FIFO means first-in, first-out with one clock [OK]

Common Mistakes:

• Confusing synchronous with asynchronous FIFO
• Thinking FIFO generates clocks
• Mixing FIFO with analog-to-digital conversion

2. Which VHDL signal type is typically used for the FIFO write pointer in a synchronous FIFO?

easy

A. std_logic_vector

B. integer

C. boolean

D. real

Solution

1. Step 1: Identify pointer representation

   Write pointers are usually binary counters represented as vectors.

2. Step 2: Choose appropriate type

   std_logic_vector is used to represent binary numbers in VHDL.

3. Final Answer:

   std_logic_vector -> Option A

4. Quick Check:

   Write pointer = std_logic_vector [OK]

Hint: Pointers are binary, so use std_logic_vector [OK]

Common Mistakes:

• Using integer which is less hardware-friendly
• Using boolean which can't count multiple bits
• Using real which is for floating-point numbers

3. Given a synchronous FIFO with depth 4, write pointer at "10" (binary 2), read pointer at "01" (binary 1), and count = 2, what happens if write enable is high and FIFO is not full?

medium

A. Write pointer resets to 0 without writing data

B. Data is written at position 1, write pointer increments to 2, count becomes 3

C. Data is not written because FIFO is full

D. Data is written at position 2, write pointer increments to 3, count becomes 3

Solution

1. Step 1: Check FIFO status

   Count is 2, depth is 4, so FIFO is not full.

2. Step 2: Write operation effect

   Data writes at write pointer position 2, pointer increments to 3, count increments to 3.

3. Final Answer:

   Data is written at position 2, write pointer increments to 3, count becomes 3 -> Option D

4. Quick Check:

   Write enabled + not full = write and increment [OK]

Hint: Write pointer points where data writes; count increments if not full [OK]

Common Mistakes:

• Writing at read pointer instead of write pointer
• Not incrementing count after write
• Assuming FIFO is full incorrectly

4. Identify the error in this VHDL snippet for a synchronous FIFO write process:

process(clk)
begin
  if rising_edge(clk) then
    if (write_enable = '1') and (not full) then
      fifo_mem(write_ptr) <= data_in;
      write_ptr <= write_ptr + 1;
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. write_ptr and count signals are not wrapped around FIFO depth

B. Missing reset condition for write_ptr

C. Data is written even when FIFO is full

D. Process is not sensitive to write_enable

Solution

1. Step 1: Analyze pointer increment logic

   write_ptr increments without wrapping back to zero at FIFO depth limit.

2. Step 2: Understand FIFO pointer behavior

   Write pointer must wrap around to zero after reaching max depth to avoid overflow.

3. Final Answer:

   write_ptr and count signals are not wrapped around FIFO depth -> Option A

4. Quick Check:

   Pointer wrap-around needed to avoid overflow [OK]

Hint: Always wrap pointers modulo FIFO depth [OK]

Common Mistakes:

• Ignoring pointer wrap-around causing overflow
• Assuming reset is mandatory in this snippet
• Confusing sensitivity list with process behavior

5. You want to design a synchronous FIFO with depth 8 and 4-bit data width. Which of the following VHDL design choices correctly ensures no data overwrite and proper empty/full detection?

hard

A. Use 3-bit write and read pointers with a count signal; check full when count = 7 and empty when count = 0

B. Use 4-bit write and read pointers without count; check full when write_ptr = read_ptr and empty when write_ptr = read_ptr

C. Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr

D. Use 4-bit write and read pointers with count; check full when count = 15 and empty when count = 0

Solution

1. Step 1: Determine pointer size

   Depth 8 requires 3-bit pointers (since 2^3=8).

2. Step 2: Understand full/empty detection without count

   Full when write pointer is one less than read pointer (circular), empty when equal.

3. Step 3: Evaluate options

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr correctly uses 3-bit pointers without count and proper full/empty logic.

4. Final Answer:

   Use 3-bit write and read pointers without count; check full when write_ptr + 1 = read_ptr and empty when write_ptr = read_ptr -> Option C

5. Quick Check:

   Pointer wrap + compare = full/empty detection [OK]

Hint: Use pointer difference for full/empty without count [OK]

Common Mistakes:

• Using wrong pointer size for FIFO depth
• Confusing full and empty conditions
• Using count with incorrect max value