I2C controller basics in VHDL - Step-by-Step Execution

Concept Flow - I2C controller basics

Start Condition Detected

↓

Send Slave Address + R/W Bit

↓

Wait for ACK from Slave

↓

Send/Receive Data

↓

Send Stop Condition

↓

End

This flow shows the basic steps of an I2C controller: start, address, acknowledge, data transfer, and stop.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if start = '1' then
      state <= SEND_ADDRESS;
    end if;
  end if;
end process;

This VHDL snippet starts the I2C controller sending the slave address when a start signal is detected.

Execution Table

Step	Signal/Variable	Condition	Action	Output
1	start	start='0'	Wait	Idle
2	start	start='1'	Set state to SEND_ADDRESS	Begin address send
3	state	state=SEND_ADDRESS	Send slave address bits	Address bits on SDA
4	ack	ack='0' (ACK received)	Proceed to data transfer	Ready to send/receive data
5	ack	ack='1' (NACK received)	Send stop condition	Stop condition on bus
6	state	state=STOP	Release bus	Bus idle
7	start	start='0'	Idle	Idle
Exit	N/A	Stop condition sent	End transaction	Bus free

💡 Stop condition sent, transaction ends and bus is free

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 4	After Step 5	Final
start	'0'	'1'	'1'	'1'	'1'	'0'
state	IDLE	SEND_ADDRESS	SEND_ADDRESS	DATA_TRANSFER	STOP	IDLE
ack	N/A	N/A	N/A	'0' or '1'	'0' or '1'	N/A

Key Moments - 3 Insights

Why does the controller wait for an ACK after sending the address?

The controller waits for an ACK (ack='0') to confirm the slave received the address. If NACK (ack='1') is received, it stops the transaction (see execution_table step 4 and 5).

What happens if the start signal is not detected?

If start='0', the controller stays idle and does not send any data (see execution_table step 1 and 7).

Why is the stop condition important at the end?

The stop condition releases the bus so other devices can use it. Without it, the bus stays busy (see execution_table step 5 and 6).

Visual Quiz - 3 Questions

Look at the execution table, what is the state after the start signal becomes '1'?

A DATA_TRANSFER

B IDLE

C SEND_ADDRESS

D STOP

💡 Hint

Check the 'state' column after step 2 in the execution_table.

At which step does the controller send the stop condition if a NACK is received?

A Step 3

B Step 5

C Step 4

D Step 6

💡 Hint

Look for the row where ack='1' (NACK) triggers sending stop condition in the execution_table.

If the start signal stays '0', what will be the output state according to variable_tracker?

A IDLE

B DATA_TRANSFER

C SEND_ADDRESS

D STOP

💡 Hint

Check the 'start' and 'state' values at start and final columns in variable_tracker.

Concept Snapshot

I2C controller basics in VHDL:
- Detect start condition to begin
- Send 7-bit slave address + R/W bit
- Wait for ACK from slave
- Send or receive data bytes
- Send stop condition to end
- State machine controls these steps
- ACK/NACK controls flow
- Stop releases the bus

Full Transcript

This visual execution shows how an I2C controller works in VHDL. It starts when the start signal is detected. Then it sends the slave address and waits for an acknowledgment (ACK) from the slave device. If ACK is received, it proceeds to data transfer. If NACK is received, it sends a stop condition to end the transaction. The stop condition releases the bus for other devices. Variables like 'start', 'state', and 'ack' change step by step to control the process. This stepwise flow helps beginners see how the controller moves through states and handles signals.

Practice

1. What are the two main signals controlled by an I2C controller in VHDL?

easy

A. CLK and RESET

B. TX and RX

C. MOSI and MISO

D. SCL (clock) and SDA (data)

Solution

1. Step 1: Understand I2C communication basics

   I2C uses two wires: one for clock (SCL) and one for data (SDA).

2. Step 2: Identify signals controlled by the controller

   The I2C controller manages these two lines to send and receive data.

3. Final Answer:

   SCL (clock) and SDA (data) -> Option D

4. Quick Check:

   I2C signals = SCL and SDA [OK]

Hint: Remember: I2C always uses clock and data lines [OK]

Common Mistakes:

• Confusing I2C signals with SPI signals
• Thinking TX/RX are used in I2C
• Mixing up clock and reset signals

2. Which VHDL statement correctly declares the SDA line as an output signal in an I2C controller?

easy

A. signal SDA : out std_logic;

B. signal SDA : in std_logic;

C. signal SDA : buffer std_logic;

D. signal SDA : inout std_logic;

Solution

1. Step 1: Recall VHDL signal directions

   Output signals are declared with the keyword 'out'.

2. Step 2: Match SDA line direction

   SDA is controlled by the I2C controller to send data, so it must be 'out'.

3. Final Answer:

   signal SDA : out std_logic; -> Option A

4. Quick Check:

   Output signal = 'out' [OK]

Hint: Output signals use 'out' keyword in VHDL [OK]

Common Mistakes:

• Using 'in' instead of 'out' for output signals
• Confusing 'buffer' and 'out' keywords
• Using 'inout' when only output is needed

3. Given this VHDL snippet for generating a start condition in I2C, what is the value of SDA after execution?

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '1';
    SCL <= '1';
    SDA <= '0'; -- start condition
  end if;
end process;

medium

A. '1'

B. '0'

C. Undefined (multiple assignments in one clock)

D. Remains previous value

Solution

1. Step 1: Analyze signal assignments in process

   Within the same clock edge, SDA is first set to '1', then immediately to '0'.

2. Step 2: Understand signal assignment behavior in VHDL

   Last assignment in the process overrides previous ones, so SDA becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Last assignment wins = '0' [OK]

Hint: Last signal assignment in process sets final value [OK]

Common Mistakes:

• Assuming first assignment sticks
• Thinking multiple assignments cause error
• Ignoring VHDL signal update rules

4. Identify the error in this VHDL code snippet for generating a stop condition in I2C:

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '0';
    SCL <= '1';
    SDA <= '1'; -- stop condition
  end if;
end process;

medium

A. SDA should be set to '1' before SCL is '1'

B. No error, code is correct

C. Multiple assignments to SDA in one clock cause conflict

D. Stop condition requires SDA to go low, not high

Solution

1. Step 1: Review SDA assignments in the process

   SDA is assigned '0' then '1' in the same clock cycle.

2. Step 2: Understand VHDL signal assignment rules

   Multiple assignments to the same signal in one clock can cause unexpected behavior or synthesis issues.

3. Final Answer:

   Multiple assignments to SDA in one clock cause conflict -> Option C

4. Quick Check:

   Multiple assignments = conflict [OK]

Hint: Avoid multiple assignments to same signal in one clock [OK]

Common Mistakes:

• Ignoring multiple assignments problem
• Confusing start and stop condition logic
• Assuming code runs without synthesis warnings

5. You want to design an I2C controller in VHDL that sends a start condition, then transmits 8 bits of data, and finally sends a stop condition. Which sequence of signal changes correctly represents this process?

hard

A. SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop)

B. SDA goes low to high while SCL is low (start), then data bits sent on SDA with SCL low, then SDA goes high to low while SCL is low (stop)

C. SCL stays low throughout, SDA toggles for start, data, and stop

D. SDA and SCL both toggle randomly during start, data, and stop

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls from high to low while SCL is high. Stop condition: SDA rises from low to high while SCL is high.

2. Step 2: Understand data transmission timing

   Data bits are sent on SDA line while toggling SCL clock line to synchronize bits.

3. Step 3: Match sequence to options

   SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop) correctly describes the start, data, and stop signal changes.

4. Final Answer:

   Start: SDA high to low while SCL high, data sent with SCL toggling, stop: SDA low to high while SCL high -> Option A

5. Quick Check:

   Start/stop conditions require SDA change while SCL high [OK]

Hint: Start/stop change SDA only when SCL is high [OK]

Common Mistakes:

• Changing SDA when SCL is low for start/stop
• Not toggling SCL during data bits
• Confusing start and stop signal directions