I2C controller basics in VHDL - Cheat Sheet & Quick Revision

Recall & Review

beginner

What does I2C stand for and what is its primary use?

I2C stands for Inter-Integrated Circuit. It is a communication protocol used to connect low-speed devices like sensors and microcontrollers using just two wires: SDA (data) and SCL (clock).

beginner

In an I2C controller, what are the two main signals and their roles?

The two main signals are SDA (Serial Data Line) which carries the data, and SCL (Serial Clock Line) which synchronizes the data transfer between devices.

beginner

What is the role of the start and stop conditions in I2C communication?

The start condition signals the beginning of a data transfer, and the stop condition signals the end. They help devices know when communication starts and stops on the shared bus.

intermediate

How does an I2C controller acknowledge data reception?

After receiving each byte, the receiver sends an ACK (acknowledge) bit by pulling the SDA line low during the 9th clock pulse to confirm successful reception.

intermediate

What is the typical role of an I2C controller implemented in VHDL?

An I2C controller in VHDL manages the timing and control signals to send and receive data over the I2C bus, handling start/stop conditions, data bits, and acknowledgments automatically.

Which two lines are used in I2C communication?

A SDA and SCL

B TX and RX

C MOSI and MISO

D CLK and DATA

I2C uses SDA (data) and SCL (clock) lines for communication.

What does the start condition in I2C do?

A Signals the end of communication

B Signals the beginning of communication

C Sends data byte

D Sends acknowledgment

The start condition tells all devices on the bus that a communication session is starting.

How does the receiver acknowledge data in I2C?

A By sending a stop condition

B By sending a start condition

C By pulling SDA low during the 9th clock pulse

D By releasing the SCL line

The receiver pulls SDA low during the 9th clock pulse to acknowledge receipt.

In VHDL, what is the main task of an I2C controller?

A Manage timing and control signals for I2C communication

B Generate random data

C Control PWM signals

D Handle Ethernet packets

The I2C controller manages start/stop conditions, data bits, and acknowledgments on the I2C bus.

What is the role of the SCL line in I2C?

A Resets the bus

B Carries the data bits

C Sends acknowledgment bits

D Provides the clock signal to synchronize data transfer

SCL is the clock line that synchronizes data transfer between devices.

Explain the basic operation of an I2C controller and the role of SDA and SCL lines.

Think about how devices talk and listen on the two wires.

Describe how an I2C controller implemented in VHDL manages communication on the bus.

Focus on the controller's tasks to keep communication smooth and correct.

Practice

1. What are the two main signals controlled by an I2C controller in VHDL?

easy

A. CLK and RESET

B. TX and RX

C. MOSI and MISO

D. SCL (clock) and SDA (data)

Solution

1. Step 1: Understand I2C communication basics

   I2C uses two wires: one for clock (SCL) and one for data (SDA).

2. Step 2: Identify signals controlled by the controller

   The I2C controller manages these two lines to send and receive data.

3. Final Answer:

   SCL (clock) and SDA (data) -> Option D

4. Quick Check:

   I2C signals = SCL and SDA [OK]

Hint: Remember: I2C always uses clock and data lines [OK]

Common Mistakes:

• Confusing I2C signals with SPI signals
• Thinking TX/RX are used in I2C
• Mixing up clock and reset signals

2. Which VHDL statement correctly declares the SDA line as an output signal in an I2C controller?

easy

A. signal SDA : out std_logic;

B. signal SDA : in std_logic;

C. signal SDA : buffer std_logic;

D. signal SDA : inout std_logic;

Solution

1. Step 1: Recall VHDL signal directions

   Output signals are declared with the keyword 'out'.

2. Step 2: Match SDA line direction

   SDA is controlled by the I2C controller to send data, so it must be 'out'.

3. Final Answer:

   signal SDA : out std_logic; -> Option A

4. Quick Check:

   Output signal = 'out' [OK]

Hint: Output signals use 'out' keyword in VHDL [OK]

Common Mistakes:

• Using 'in' instead of 'out' for output signals
• Confusing 'buffer' and 'out' keywords
• Using 'inout' when only output is needed

3. Given this VHDL snippet for generating a start condition in I2C, what is the value of SDA after execution?

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '1';
    SCL <= '1';
    SDA <= '0'; -- start condition
  end if;
end process;

medium

A. '1'

B. '0'

C. Undefined (multiple assignments in one clock)

D. Remains previous value

Solution

1. Step 1: Analyze signal assignments in process

   Within the same clock edge, SDA is first set to '1', then immediately to '0'.

2. Step 2: Understand signal assignment behavior in VHDL

   Last assignment in the process overrides previous ones, so SDA becomes '0'.

3. Final Answer:

   '0' -> Option B

4. Quick Check:

   Last assignment wins = '0' [OK]

Hint: Last signal assignment in process sets final value [OK]

Common Mistakes:

• Assuming first assignment sticks
• Thinking multiple assignments cause error
• Ignoring VHDL signal update rules

4. Identify the error in this VHDL code snippet for generating a stop condition in I2C:

process(clk)
begin
  if rising_edge(clk) then
    SDA <= '0';
    SCL <= '1';
    SDA <= '1'; -- stop condition
  end if;
end process;

medium

A. SDA should be set to '1' before SCL is '1'

B. No error, code is correct

C. Multiple assignments to SDA in one clock cause conflict

D. Stop condition requires SDA to go low, not high

Solution

1. Step 1: Review SDA assignments in the process

   SDA is assigned '0' then '1' in the same clock cycle.

2. Step 2: Understand VHDL signal assignment rules

   Multiple assignments to the same signal in one clock can cause unexpected behavior or synthesis issues.

3. Final Answer:

   Multiple assignments to SDA in one clock cause conflict -> Option C

4. Quick Check:

   Multiple assignments = conflict [OK]

Hint: Avoid multiple assignments to same signal in one clock [OK]

Common Mistakes:

• Ignoring multiple assignments problem
• Confusing start and stop condition logic
• Assuming code runs without synthesis warnings

5. You want to design an I2C controller in VHDL that sends a start condition, then transmits 8 bits of data, and finally sends a stop condition. Which sequence of signal changes correctly represents this process?

hard

A. SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop)

B. SDA goes low to high while SCL is low (start), then data bits sent on SDA with SCL low, then SDA goes high to low while SCL is low (stop)

C. SCL stays low throughout, SDA toggles for start, data, and stop

D. SDA and SCL both toggle randomly during start, data, and stop

Solution

1. Step 1: Recall I2C start and stop conditions

   Start condition: SDA falls from high to low while SCL is high. Stop condition: SDA rises from low to high while SCL is high.

2. Step 2: Understand data transmission timing

   Data bits are sent on SDA line while toggling SCL clock line to synchronize bits.

3. Step 3: Match sequence to options

   SDA goes from high to low while SCL is high (start), then data bits sent on SDA with SCL toggling, then SDA goes low to high while SCL is high (stop) correctly describes the start, data, and stop signal changes.

4. Final Answer:

   Start: SDA high to low while SCL high, data sent with SCL toggling, stop: SDA low to high while SCL high -> Option A

5. Quick Check:

   Start/stop conditions require SDA change while SCL high [OK]

Hint: Start/stop change SDA only when SCL is high [OK]

Common Mistakes:

• Changing SDA when SCL is low for start/stop
• Not toggling SCL during data bits
• Confusing start and stop signal directions